WorksheetsComputer Organization and Architecture
Total questions: 20
Worksheet time: 10mins
The main components (or basic units) of a computer system are
Input/Output unit
Central Process Unit (CPU)
Memory unit (Storage unit)
All the above
The device used to fetch (or bring) instructions and data into a computer system is called
ALU
Control Unit
Input Device
Output Device
The instruction, Add #45,R1 does _______
Adds the value of 45 to the address of R1 and stores 45 in that address
Adds 45 to the value of R1 and stores it in R1
Finds the memory location 45 and adds that content to that of R1
None of the mentioned
The addressing mode/s, which uses the PC instead of a general purpose register is ______
Indexed with offset
Relative
Direct
Both Indexed with offset and direct
In CISC architecture most of the complex instructions are stored in _____
CMOS
Register
Transistors
Diodes
________ are the different type/s of generating control signals.
Hardwired
Micro-instruction
Micro-programmed
Both Micro-programmed and Hardwired
What is the full form of ISA?
Industry Standard Architecture
International Standard Architecture
International American Standard
None of the mentioned
During a write operation if the required block is not present in the cache then ______ occurs.
Write miss
Write latency
Write hit
Write delay
The bit used to indicate whether the block was recently used or not is _______
Reference bit
Dirty bit
Control bit
Idol bit
The techniques which move the program blocks to or from the physical memory is called as ______
Paging
Virtual memory organization
Overlays
Framing
______ translates the logical address into a physical address.
MMU
Translator
Compiler
Linker
Each stage in pipelining should be completed within ___________ cycle.
1
2
3
4
The situation wherein the data of operands are not available is called ______
Data hazard
Stock
Deadlock
Structural hazard
The DMA transfers are performed by a control circuit called as __________
Device interface
DMA controller
Data controller
Overlooker
After the completion of the DMA transfer, the processor is notified by __________
Acknowledge signal
Interrupt signal
WMFC signal
None of the mentioned
_____ BUS arbitration approach uses the involvement of the processor.
Centralised arbitration
Distributed arbitration
Random arbitration
All of the mentioned
The key features of the SCSI BUS are _________
The cost effective connective media
The ability overlap data transfer requests
The highly efficient data transmission
None of the mentioned
The BSY signal signifies _________
The BUs is busy
The controller is busy
The Initiator is busy
The Target is Busy
The sampling process in speaker output is a ________ process.
Asynchronous
Synchronous
Isochronous
None of the mentioned
The I/O devices form the _____ of the tree structure.
Leaves
Subordinate roots
Left subtrees
Right subtrees
