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Computer Organization and Architecture

Total questions: 20

Worksheet time: 10mins

Name
Class
Date
1.

The main components (or basic units) of a computer system are

a)

Input/Output unit

b)

Central Process Unit (CPU)

c)

Memory unit (Storage unit)

d)

All the above

2.

The device used to fetch (or bring) instructions and data into a computer system is called

a)

ALU

b)

Control Unit

c)

Input Device

d)

Output Device

3.

The instruction, Add #45,R1 does _______

a)

Adds the value of 45 to the address of R1 and stores 45 in that address

b)

Adds 45 to the value of R1 and stores it in R1

c)

Finds the memory location 45 and adds that content to that of R1

d)

None of the mentioned

4.

The addressing mode/s, which uses the PC instead of a general purpose register is ______

a)

Indexed with offset

b)

Relative

c)

Direct

d)

Both Indexed with offset and direct

5.

In CISC architecture most of the complex instructions are stored in _____

a)

CMOS

b)

Register

c)

Transistors

d)

Diodes

6.

________ are the different type/s of generating control signals.

a)

Hardwired

b)

Micro-instruction

c)

Micro-programmed

d)

Both Micro-programmed and Hardwired

7.

What is the full form of ISA?

a)

Industry Standard Architecture

b)

International Standard Architecture

c)

International American Standard

d)

None of the mentioned

8.

During a write operation if the required block is not present in the cache then ______ occurs.

a)

Write miss

b)

Write latency

c)

Write hit

d)

Write delay

9.

The bit used to indicate whether the block was recently used or not is _______

a)

Reference bit

b)

Dirty bit

c)

Control bit

d)

Idol bit

10.

The techniques which move the program blocks to or from the physical memory is called as ______

a)

Paging

b)

Virtual memory organization

c)

Overlays

d)

Framing

11.

______ translates the logical address into a physical address.

a)

MMU

b)

Translator

c)

Compiler

d)

Linker

12.

Each stage in pipelining should be completed within ___________ cycle.

a)

1

b)

2

c)

3

d)

4

13.

The situation wherein the data of operands are not available is called ______

a)

Data hazard

b)

Stock

c)

Deadlock

d)

Structural hazard

14.

The DMA transfers are performed by a control circuit called as __________

a)

Device interface

b)

DMA controller

c)

Data controller

d)

Overlooker

15.

After the completion of the DMA transfer, the processor is notified by __________

a)

Acknowledge signal

b)

Interrupt signal

c)

WMFC signal

d)

None of the mentioned

16.

_____ BUS arbitration approach uses the involvement of the processor.

a)

Centralised arbitration

b)

Distributed arbitration

c)

Random arbitration

d)

All of the mentioned

17.

The key features of the SCSI BUS are _________

a)

The cost effective connective media

b)

The ability overlap data transfer requests

c)

The highly efficient data transmission

d)

None of the mentioned

18.

The BSY signal signifies _________

a)

The BUs is busy

b)

The controller is busy

c)

The Initiator is busy

d)

The Target is Busy

19.

The sampling process in speaker output is a ________ process.

a)

Asynchronous

b)

Synchronous

c)

Isochronous

d)

None of the mentioned

20.

The I/O devices form the _____ of the tree structure.

a)

Leaves

b)

Subordinate roots

c)

Left subtrees

d)

Right subtrees