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80386 processor and Insatruction set

Total questions: 40

Worksheet time: 10mins

Name
Class
Date
1.

The memory management of 80386 supports

a)

virtual memory

b)

paging

c)

Four level of protection

d)

All of above

2.

The Unit that increases the speed of all shift and rotate operation is------

a)

Memory management unit

b)

execution unit

c)

instruction unit

d)

barrel Shifter

3.

The memory management unit consists of_____

a)

segmentation unit

b)

paging unit

c)

segmentation and paging unit

d)

none

4.

The central processing unit has a sub-division of

a)

memory unit and control unit

b)

memory unit and ALU

c)

execution unit and instruction unit

d)

execution unit and memory unit

5.

The unit that is used for handling data, and calculate offset address is----------

a)

memory management unit

b)

execution unit

c)

instruction unit

d)

bus interface unit

6.

What feature of the 80386 memory management system provides enhanced security?

a)

Virtual memory

b)

Paging

c)

Four levels of protection

d)

Memory segmentation

7.

The operation that can be performed on segments in 80386 real mode is-----

a)

Read

b)

Write

c)

Execute

d)

All of above

8.

The linear address is calculated by------

a)

effective address + segment base address

b)

effective address – segment base address

c)

effective address + physical address

d)

effective address – physical address

9.

What does the last instruction of each subroutine that transfer the control to the instruction in the calling program with temporary address storage , called as?

a)

jump to subroutine

b)

branch to subroutine

c)

return from subroutine

d)

call subroutine

10.

The mnemonic that is placed before the arithmetic operation is performed is

a)

AAA

b)

AAS

c)

AAM

d)

AAD

11.

In the RCL instruction, the contents of the destination operand undergoes function as--

a)

carry flag is pushed into LSB and MSB is pushed into carry flag

b)

carry flag is pushed into MSB and LSB is pushed into carry flag

c)

auxiliary flag is pushed into LSB and MSB is pushed into carry flag

d)

parity flag is pushed into MSB and LSB is pushed into carry flag

12.

The instruction that is used as prefix to an instruction to execute it repeatedly until the CX register becomes zero is

a)

SCAS

b)

REP

c)

CMPS

d)

STOS

13.

The instructions that are used to call a subroutine from a main program and return to the main program after execution of called function are---

a)

CALL, JMP

b)

JMP, IRET

c)

CALL, RET

d)

JMP, RET

14.

The instruction that unconditionally transfers the control of execution to the specified address is

a)

CALL

b)

JMP

c)

RET

d)

IRET

15.

The 80386DX is a processor that supports

a)

8-bit data operand

b)

16-bit data operand

c)

32-bit data operand

d)

all of the mentioned

16.

The 80386DX has an address bus of

a)

8 address lines

b)

16 address lines

c)

32 address lines

d)

64 address lines

17.

80386DX is available in a grid array package of

a)

64 pin

b)

128 pin

c)

132 pin

d)

142 pin

18.

The 80386 in its protected mode, in its virtual mode of operation, can run the applications of---

a)

8086

b)

80286

c)

80287

d)

80387

19.

The 80386 in protected mode, supports all software written for

a)

8086 and 80287

b)

80286 and 80287

c)

80287 and 80387

d)

80286 and 8086

20.

The flag bits that indicate the privilege level of current IO operations are

a)

virtual mode flag bits

b)

IOPL flag bits

c)

resume flag bits

d)

none of the mentioned

21.

Which of the following is not a scale factor of addressing modes of 80386?

a)

2

b)

4

c)

6

d)

8

22.

Contents of an index register are multiplied by a scale factor that may be added further to get the operand offset in

a)

base scaled indexed mode

b)

scaled indexed mode

c)

indexed mode

d)

none of the mentioned

23.

Contents of an index register are multiplied by a scale factor and then added to base register to get the operand offset in

a)

base scaled indexed mode

b)

scaled indexed mode

c)

indexed mode

d)

none of the mentioned

24.

In based scaled indexed mode with displacement mode, the contents of an index register are multiplied by a scale factor and are added to

a)

base register

b)

displacement

c)

base register and displacement

d)

None

25.

The following statement of ALP is an example of ------

MOV EBX, [EDX*4] [ECX]

a)

base scaled indexed mode

b)

scaled indexed mode

c)

indexed mode

d)

based scaled indexed mode with displacement mode

26.

A decimal digit can be represented by

a)

unsigned integer

b)

signed integer

c)

unpacked BCD

d)

packed BCD

27.

The 80386DX is a processor that supports:

a)


8-bit data operand

b)


16-bit data operand

c)


32-bit data operand

d)

All of above

28.

The instructions that are used for reading an input port and writing an output port respectively are

a)

MOV,XCHG

b)

MOV,IN

c)

IN,MOV

d)

IN,OUT

29.


The instruction that loads the AH register with the lower byte of the flag register is

a)

SAHF

b)

AH

c)

LAHF

d)

PUSHF

30.

The instruction that pushes the flag register on to the stack is

a)

PUSH

b)

POP

c)

PUSHF

d)

POPF

31.

The instruction that subtracts 1 from the contents of the specified register/memory location is

a)

INC

b)

SBB

c)

SUBB

d)

DEC

32.

In general, the destination operand of an instructon can be

a)

Memory location

b)

register

c)

immediate data

d)

Memory location and regiser

33.

If the data is present in a register and it is referred using the particular register, then it is

a)


direct addressing mode

b)

register addressing mode

c)


indexed addressing mode

d)

none of above

34.


The instruction, MOV AX,[BX]

is an example of

a)

direct addressing mode

b)


register addressing mode

c)

register relative addressing mode

d)


register indirect addressing mode

35.

80386 support overall ___ addressing modes to facilitate efficient execution of higher level language programs.

a)

9

b)

10

c)

11

d)

12

36.

The 80386 provides how many General Purpose Registers (GPRs)?

a)

10

b)

14

c)

16

d)

8

37.

The instruction XCHG AX, BX will:

a)

Add AX and BX

b)

Swap AX and BX

c)

Move BX to AX

d)

Clear BX

38.

The instruction ADC AX, BX performs:

a)

AX + BX

b)

AX + BX + CF

c)

AX – BX

d)

BX – AX

39.

The instruction IRET is used to:

a)

Return from subroutine

b)

Return from interrupt service routine

c)

Jump to interrupt vector

d)

Reset flags

40.

The size of EFLAGS register in 80386 is:

a)

64

b)

32

c)

8

d)

None