WorksheetsCSA Final (csa_13-27)
Total questions: 102
Worksheet time: 51mins
Choose the physical characteristic(s) of disk systems
Head Mechanism
Platters
Disk Size
Sides
Disk system implementstion
Choose the components of SSD
Controller
Addressing
Data buffer/cache
Data size
Memory hierarchy
Choose the legal name(s) in assembly
@variable_name
variable?
variable&name
variable name
1variable
In two-operand instruction, the first operand is source and the second operand is destination
true
false
An instruction may have one or more operands
true
false
In assembly language you can express data only in binary and decimal
true
false
Which symbol you should use to leave the variable uninitialized
(a)
In assembly language, you can skip the name of variable
true
false
Choose the correct syntax of variable declaration in assembly
variable_name type initial_valuee
type variable_name initial_vaule
variable_name type initial_value
type initial_value variable_name
Choose the definition of code segment in assembly
Contains a program's instructions
A block of memory to store a stack
All variable definitions
Choose the definition of data segment in assembly
All variable definitions
A block of memory to store a stack
Contains a program's instructions
Choose the definition of stack segment in assembly
A block of memory to store a stack
All variable definitions
Contains a program's instructions
There is no memory allocated for constants in assembly language
true
false
Which keyword you should use in order to define a constant in assembly language
DD
CONST
EQ
DW
In assembly statement name and comment are mandatory
true
false
There are 3 approaches of deadlock avoidance
true
false
There are 2 policies of deadlock prevention
true
false
Choose the correct approach for the following definition "involves recognizing when deadlock has occurred, and trying to recover"
Deadlock detection and recovery
Deadlock avoidance
Deadlock prevention
Choose the correct approach for the following definition "involves making dynamic choices that guarantee prevention"
Deadlock avoidance
Deadlock prevention
Deadlock detection and recovery
Choose the correct approach for the following definition "adopting a static policy that disallows one of the four conditions above"
Deadlock prevention
Deadlock detection and recovery
Deadlock avoidance
There are 4 approaches of dealing with deadlock
true
false
Choose the correct answer for the following definition "A closed chain of processes exists, such that each process is blocked waiting for a resource held by another process in the set"
Mutual exclusion
No preemption
Hold and wait
Choose the correct answer for the following definition: "No process can be forced to release a resource"
Mutual exclusion
Hold and wait
Circular wait
Choose the correct answer for the following definition "A process may hold some resources while waiting for others"
Circular wait
No pre-emption
Mutual exclusion
Choose the correct answer for the following definition "Only one process may use a resource at one time"
Circular wait
No preemption
Mutual exclusion
Hold and wait
What is the deadlock?
Permanent blocking of a set of processes that either compete for global resources or communicate with each other
Interleaving of processes in time to give the appearance of simultaneous execution
When one process is inside a critical section of code, oth-
er processes must be prevented from entering that section o Processes "communicate" via global counters that are initialized to a positive integer and that can be accessed only through two atomic operations
Deadlock occurs when each process in the set is blocked awaiting an event that can be triggered only by another blocked process in the set
true
false
In which of the following approaches there is no shared data?
Mutual exclusion
Monitors
Semaphores
Choose the correct answer for the following definition "Synchronization between processes is defined by the blocking policy attached to the sending and receiving of messages"
Mutual exclusion
Monitors
Semaphores
Monitors are similar to classes in java and has methods and fields
true
false
In atomic operations semSignal(x) and semWait(x), what is the 'x'?
The number of processes that can execute critical section
The number of processes
The number of monitors
No correct answer
When using semaphores, processes communicate using messages
true
false
We can implement mutex through the OS or using programming languages
true
false
Choose the correct answer for the following definition "When one process is inside a critical section of code, other processes must be prevented from entering that section"
Mutual exclusion
Semaphores
Monitors
Message passing
Critical section
Moore's law: "The cost of a chip has remained virtually unchanged during this period of rapid growth in density. This means that the cost of computer logic and memory circuitry has increasing at a dramatic rate"
true
false
What is a Latency?
is time for a single access - Main memory latency is usually >> than processor cycle time
is the number of accesses per unit time - If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
is amount of data that can be in flight at the same time (Little's Law)
Least Recently Used (LRU):
cache state must be updated on every access
Used in highly associative caches
FIFO with exception for most recently used block(s)
Reduce Miss Rate: Large Cache Size. Empirical Rule of Thumb:
If cache size is doubled, miss rate usually drops by about 2
Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
None of them
Reduce Miss Rate: High Associativity. Empirical Rule of Thumb:
Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
If cache size is doubled, miss rate usually drops by about 2
None of them
Exploit temporal locality:
by remembering the contents of recently accessed locations
by fetching blocks of data around recently accessed locations
None of them
Exploit spatial locality:
by fetching blocks of data around recently accessed locations
by remembering the contents of recently accessed locations
None of them
What is the access time?
Time between when a read is requested and when the desired word arrives
The minimum time between requests to memory.
Describes the technology inside the memory chips and those innovative, internal organizations
None of them
What is the cycle time?
The minimum time between requests to memory.
Time between when a read is requested and when the desired word arrives
The maximum time between requests to memory.
None of them
What is kernel process?
Provide at least two modes, indicating whether the running process is a user process or an operating system process
Provide at least five modes, indicating whether the running process is a user process or an operating system process
Provide a portion of the processor state that a user process can use but not write
None of them
How many physical characteristics of disk systems are there?
4
5
2
3
6
How many categories of process management are there?
3
2
4
5
1
According to Moore's law, has the cost of a chip remained virtually unchanged during the period of rapid growth in density?
False
True
Concurrency offers genuine simultaneous execution
True
False
How many approaches of mutex implementation are there?
3
4
2
5
1
Name field of assembly statement is not case sensitive
True
False
Compulsory -
first-reference to a block, occur even with infinite cache
misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
Parallelism is interleaving of processes in time to give the appearance of simultaneous execution
True
False
SSD stands for
Solid State Drive
Solid State Driver
Speed State Drive
Speed State Driver
The basic element of a semiconductor memory is:
Memory cell
Cache memory
RAM
DRAM
The use of the _______ defines the third generation of computers.
Small and medium-scale integration
Transistor
Vacuum tube
Large-scale integration
Very-large-scale integration
The use of the _______ defines the first generation of computers.
Vacuum tube
Transistor
Small and medium-scale integration
Processor can simultaneously work on multiple instructions. What is this technique called?
Pipelining
Branch prediction
Data flow analysis
Speculative execution
None of the above
The RAID scheme consists of 7 levels
True
False
In concurrency optimal allocation of resources is difficult
True
False
ENIAC stands for:
Electronic Numerical Integrator and Computer
Electronic Nuclear Integrator and Computer
Encapsulation Numerical Integrator and Commerce
Encapsulation Numerical Integrator and Computer
Electronic Numerical Integer and Computer
Memory is organized into units of data, called records; access must be made in a specific linear sequence
Sequential access
Word
Addressable units
Unit of transfer
Direct access
How many deadlock recovery algorithms are there?
4
3
2
5
1
In concurrency, locating programming errors can't be difficult, because the contexts in which errors occur cannot always be reproduced easily
True
False
RAID stands for
Redundant Array Independent Disk
Random Access Integral Disk
Redundant Access Integral Disk
Random Array Independent Disk
Redundant Access Independent Disk
Employed to hold temporarily the right-hand instruction from a word in memory
Instruction buffer register (IBR)
Memory buffer register (MBR)
Memory address register (MAR)
Instruction register (IR)
Program counter (PC)
SSD is over 10 times faster than the spinning disks in HDD
True
False
Choose the correct answer for the following definition "multiple processes on a system with multiple processors"
Multiprocessing
Multiprogramming
Distributed processing
How many policy conditions for deadlock to be possible are there?
3
4
2
5
1
SSDs are more susceptible to physical shock and vibration
True
False
Cache HIT:
No Write Allocate, Write Allocate
Write Through, Write Back
The use of the _______ defines the second generation of computers.
Transistor
Vacuum tube
Small and medium-scale integration
Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit
Memory buffer register (MBR)
Memory address register (MAR)
Instruction register (IR)
Instruction buffer register (IBR)
Program counter (PC)
Contains the address of the next instruction pair to be fetched from memory
Program counter (PC)
Memory buffer register (MBR)
Memory address register (MAR)
Instruction register (IR)
Instruction buffer register (IBR)
the correct answer for the following definition "When one process is inside a critical section of code, other processes must be prevented from entering that section"
Mutual exclusion
Semaphores
Monitors
Message passing
Critical section
For random-access memory, this is the time it takes to perform a read or write operation
Access time
Memory cycle time
Transfer rate
Performance
All of the above
A processor is driven by a clock with a constant frequency f or, equivalently, a constant cycle time t, where t = 1/f:
Instruction execution rate
Instruction execution cycle
Instruction execution time
Instruction execution period
Choose the correct answer for the following definition "multiple processes on multiple systems"
Distributed processing
Multiprogramming
Multiprocessing
Choose the correct answer for the following definition "multiple processes on a system with a single processor"
Multiprogramming
Multiprocessing
Distributed processing
What does RAID stand for?
Random Array of Independent Disks
Redundant Array of Independent Disks
Redundant Array of Interoperable Disks
Random Access to Independent Disks
What occurs at Instruction fetches when we speak about Common And Predictable Memory Reference Patterns?
n loop iterations
subroutine call
vector access
Choose the component of SSD for the following definition: provides SSD device level interfacing and firmware execution
Controller
Addressing
Data buffer/cache
Error correction
Flash memory components
The time between pulses called?
Cycle time
Clock speed
Specifies the address in memory of the word to be written from or read into the MBR
Memory address register (MAR)
Memory buffer register (MBR)
Instruction register (IR)
Instruction buffer register (IBR)
Program counter (PC)
Contains the 8-bit opcode instruction being executed
Instruction register (IR)
Memory buffer register (MBR)
Memory address register (MAR)
Instruction buffer register (IBR)
Program counter (PC)
In concurrency, sharing global resources safely is difficult
True
False
Measures such as MIPS and MFLOPS have proven adequate to evaluating the performance of processors.
False
True
The "natural" unit of organization of memory
Word
Sequential access
Addressable units
Unit of transfer
Direct access
Average Memory Access Time is equal to?
Hit Time + ( Miss Rate * Miss Penalty )
Hit Time * ( Miss Rate + Miss Penalty )
Hit Time - ( Miss Rate + Miss Penalty )
Hit Time / ( Miss Rate - Miss Penalty )
Operations performed by a processor, such as fetching an instruction, decoding the instruction, performing an arithmetic operation, and so on, are governed by:
a system clock
a system processor
a clock processor
a processor
a clock
What does Moore's law state about the reduction in power and cooling requirements?
True
False
What is a Bandwidth?
a is the number of accesses per unit time - If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
is time for a single access - Main memory latency is usually >> than processor cycle time
is amount of data that can be in flight at the same time (Little's Law)
SSDs are susceptible to mechanical wear
True
False
The formula of 'Iron Law' of Processor Performance:
time/program = instruction/program * (cycles/instruction) * time/cycle
time/program = instruction/program * (cycles/instruction) + time/cycle
time/program = instruction/program + (cycles/instruction) * time/cycle
Typically all operations performed by a processor begin with the:
pulse of the clock
pulse of the processor
it begins by itself
both of clock and processor pulse
none of the above
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an "System response time" - ?
The time between when the user enters the command and the complete response is displayed
The time for the user to enter the command
The time from the reception of the response until the user begins to enter the next
What is Computer Architecture?
is the design of the abstraction/implementation layers that allow us to execute information processing applications efficiently using manufacturing technologies
is a group of computer systems and other computing hardware devices that are linked together through communication channels to facilitate communication and resource-sharing among a wide range of users
the programs used to direct the operation of a computer, as well as documentation giving instructions on how to use them
Algorithm for Cache MISS:
Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> Read block of data from main memory -> Replace victim block in cache with new block -> return copy of data from cache
Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache
What does DDR stands for?
Double data rate
Dual data rate
Double data reaction
None of them
What is a Bandwidth-Delay Product?
is amount of data that can be in flight at the same time (Little's Law)
is time for a single access - Main memory latency is usually >> than processor cycle time
is the number of accesses per unit time - If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
Cache MISS:
No Write Allocate, Write Allocate
Write Through, Write Back
Cache Hit -
Write Through - write both cache and memory, generally higher traffic but simpler to design
write cache only, memory is written when evicted, dirty bit per block avoids unnecessary write backs, more complicated
No Write Allocate - only write to main memory
Algorithm for Cache HIT:
Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> return copy of data from cache
Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache
Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
