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WorksheetsCMSC 133 - UNIT 3
Total questions: 80
Worksheet time: 40mins
What is a sign of high CPU usage when the computer is idle?
CPU usage below 10%
CPU usage above 20%
CPU usage above 80% only during heavy tasks
CPU usage fluctuates between 5% and 10%
What hazard occurs when two instructions compete for the same resource simultaneously?
Data Hazard
Structural Hazard
Control Hazard
Name Dependency
Which of the following is an example of a control hazard solution?
Register renaming
Delayed branching
Pipeline forwarding
Output dependency
What is a common cause of overheating in a computer?
Outdated software
High CPU usage
Blocked air vents
All of the above
What is a mitigation strategy for input overvoltage?
Use external filtering circuits
Employ Undervoltage protection (UVP)
Install surge suppressors
Both b and c
What is a potential sign of high CPU usage when performing tasks that are not resource-heavy?
CPU operates silently
CPU usage drops below 10%
Sluggish computer performance
Mouse responsiveness improves
What type of pipelining hazard occurs when one instruction depends on the result of a previous instruction still in the pipeline?
Structural Hazard
Data Hazard
Control Hazard
Branch Prediction
What is a key risk associated with overclocking a CPU?
Improved system cooling
Increased CPU lifespan
Reduced CPU lifespan
More efficient multitasking
Which of the following symptoms might indicate a failing CPU?
A blue screen with an error code
Increased storage capacity
Improved battery performance
Faster startup times
What is a mitigation strategy for preventing reversed polarity issues in a power supply unit (PSU)?
Utilize Undervoltage protection (UVP)
Use diodes to block reverse currents
Ensure external components are missing
Increase heat generation
What is the primary goal of Instruction-Level Parallelism (ILP)?
To reduce memory usage
To enable simultaneous execution of instructions
To minimize the number of processor cores
. To improve software reliability
Which hardware structure is responsible for keeping track of instruction completion in out-of-order execution?
Branch Predictor
Reorder Buffer (ROB)
Floating Point Unit
Instruction Decoder
What is the main drawback of speculative execution in ILP?
Increased latency in executing instructions
Lower branch prediction accuracy
Wasted energy on incorrect predictions
Reduced memory bandwidth
According to Amdahl’s Law, why are performance gains from ILP limited?
Instructions cannot always be reordered.
Serial portions of programs dominate execution time.
Memory bandwidth does not scale with cores.
Pipelines increase misprediction penalties
What type of branch predictor adapts to program behavior by tracking past branch outcomes?
Static Predictor
Tournament Predictor
Dynamic Predictor
Bimodal Predictor
Which of the following is NOT a challenge associated with scaling ILP in multi-core processors?
Memory contention between cores
Increased complexity of NUMA architectures
Limited serial portions of programs
Leakage currents in smaller process nodes
What technique minimizes the need to repeatedly fetch frequently used operations in AMD Zen microarchitecture?
Dynamic Branch Prediction
. Micro-op Cache
Reorder Buffer
Superscalar Execution
How do pipeline ushes impact processors during branch mispredictions?
They reduce energy efficiency by discarding incorrectly executed instructions.
They delay branch prediction by rerunning all instructions.
They allow parallel execution of new instructions.
They double the latency of completed instructions.
What is one way future processors aim to improve branch prediction accuracy?
Use of machine learning techniques
Static prediction of branch outcomes
Reducing the size of instruction windows
Limiting speculative execution
Which held heavily relies on ILP to process massive matrix multiplications efficiently?
High-Performance Computing
Machine Learning and AI
Gaming
Processor Cooling Technology
What is a micro-operation?
A large task performed by the ALU
The smallest functional task performed by the CPU's control unit
A method to store data in memory
An input/output device operation
What is the first phase of the instruction cycle?
Decode
Execute
Fetch
Write-back
What is the role of control signals?
To guide the CPU on what to do
To charge the computer battery
To display images on the screen
To send emails
What does the Fetch stage do?
Performs the addition of two numbers
Moves the instruction from memory to the CPU
Displays a message on the screen
Stores data in memory
What is the function of the Memory Read (MR) signal?
To save data into memory
To retrieve data from memory
To turn off the computer
To clear a register
What does a hardwired control unit use to generate control signals?
A set of instructions stored in memory
Fixed hardware circuits
Data from the internet
The user’s input
Which component performs arithmetic and logic operations in a CPU?
ALU (Arithmetic Logic Unit)
Memory
Control Bus
I/O Device
What type of control signal is used to shift the value in a register to the left?
Memory Write
Shift
Rotate
Increment
Which of the following is an example of a micro-operation?
Moving data from one register to another
Installing an operating system
Writing an email
Connecting to Wi-Fi
Micro-operations are typically executed during which CPU process?
Writing data to a file
Instruction cycle stages like Fetch, Decode, or Execute
Running an external program
Connecting to a network
Which of the following advantages of pipelining defines its efficient use of resources that can reduce overall operational costs?
Cost Effectiveness
Scalability
Faster Execution
Support for Advanced Computing Needs
How does pipelining execute multiple instructions simultaneously?
having its own set of resources to perform operations in parallelism and improve the performance of the processors
compressing them into one task to execute at the same time
distributing tasks across multiple processors
breaking down each instruction into separate, overlapping stages that allow the processor to work on different instructions at a time
Each ____ processes a new instruction as it progresses through the pipeline stages
step
processor
minute
clock cycle
At which stage of pipelining are the operands read and written to present in the instruction?
Instruction Execute
Memory Fetch
Instruction Fetch
Instruction Decode
Pipelining is a standard feature in ____ processors, which utilizes the 5-stage instruction whereas _____ processors do not support parallelism and pipelining.
RISC; CISC
. CISC; RISC
RISC; LC3
LC3; RISC
Which one of the following is NOT a data hazard?
Read after Read (RAR)
Write after Read (WAR)
Write after Write (WAW)
Read after Write (RAW)
______ occur when multiple instructions compete for the same hardware resource simultaneously, such as memory or functional units.
Control Hazard
Hardware Hazard
Structural Hazard
Data Hazard
At which stage of pipelining does the processor get instructions from memory and loads it into a special register?
Memory Access
Instruction Decode
Instruction Fetch
Write Back
The following tasks benefit pipelining’s support for advanced computing needs (high-speed computations due to its optimized nature) EXCEPT for one
Graphics processing
Artificial intelligence
Big data analysis
Optimizing hardware resources
This feature allows for minimization of idle time and improvement of execution time
Increased Throughput
Faster Execution
Scalability
Support for Advanced Computing Needs
What is included in the thread context?
Open files, global variables, and thread priority
CPU registers, stack, and program counter
CPU registers, global data, and program counter
Heap memory, thread ID, and process code
How does Thread-Level Parallelism (TLP) differ from Instruction-Level Parallelism (ILP)?
TLP focuses on reordering instructions within a single thread, while ILP uses multiple cores.
TLP relies on pipelining, whereas ILP requires shared memory multiprocessors.
TLP explicitly uses multiple threads of execution, while ILP exploits parallelism within a single thread.
TLP is implicit and handled by the compiler, while ILP is explicitly defined by the programmer.
What is a thread in the context of CPU utilization?
The smallest unit of CPU execution
A hardware feature used to execute multiple processes simultaneously
A process that runs independently with its own memory space and files
A lightweight task that shares no resources with other threads in the process.
Which of the following best describes the role of Thread-Level Parallelism (TLP) in server environments and web applications?
It limits server capabilities to reduce system overhead.
It allows servers to process only one task at a time
It enhances responsiveness and scalability by distributing tasks across multiple threads
It eliminates the need for database management in web applications.
What role do advances in compiler technologies play in TLP?
Simplifying single-thread execution
Automating the parallelization of code
Reducing the need for multi-core processors
Increasing the need for manual parallelization
Which category in Flynn’s Taxonomy is best suited for vector and matrix operations?
SISD
SIMD
MISD
MIMD
What is a key feature of MISD systems?
Executing multiple instructions on multiple datasets
Executing the same instruction on multiple datasets
Executing multiple instructions on a single dataset
Sequential execution of instructions
How does MIMD architecture handle memory?
Only shared memory
Only distributed memory
Both shared and distributed memory
No memory is shared
Which of the following is a challenge in managing thread-level parallelism (TLP) related to hardware design?
Memory Contention
Cache Coherence
Task Granularity
Real-Time Constraints
Which of the following best describes a performance limitation in thread-level parallelism (TLP) according to Amdahl's Law?
Increased synchronization overhead with higher thread counts
Diminishing returns in performance as the number of threads increases
Increased resource contention between threads
Load imbalance causes some threads to idle while others work
What is a chip multiprocessing?
Switching threads in one core
Using multiple cores on a chip
Running one thread at a time
Combining all threads into one process
What is a process?
A simple task performed by the CPU
A thread running inside the processor
A program running with its own memory and resources
A hardware feature for faster execution
What is the primary advantage of simultaneous multithreading (SMT)?
It reduces hardware complexity
It utilizes all available execution slots for maximum efficiency
It simplifies the compiler’s task
It eliminates thread-switch delays entirely
What is the key feature of threads?
Threads do not share resources
Threads run in separate processors only
Threads require no operating system support
Threads share memory and resources
What is VLIW used for?
Running multiple instructions in one word
Switching threads faster
Slowing down instructions for accuracy
Combining all threads in one process
Why is a thread switch faster than a process switch?
Threads share resources, so less data is moved
Threads run in separate cores
Processes take less memory than threads
Threads require fewer instructions
What is the main feature of blocked thread multithreading?
Running all threads together
Using a single thread for all tasks
Switching threads when one is stalled
Switching between threads every cycle
Which of the following describes a user-level thread?
Managed by the operating system
Managed by applications
Runs on separate processor
Require kernel-level support
What is a thread?
A physical core in the processor
A hardware feature for fast computing
A lightweight unit of work within a process
A program that owns resources and memory
What is the primary measure of processor performance?
Clock Frequency
Number of Threads
Instruction Complexity
Millions Instructions Per Second (MIPS)
What is a primary characteristic of superscalar processors?
Execute one instruction at a time
Utilize multiple instruction pipelines
Require only basic scheduling systems
Operate without hardware Dependencies
What enables superscalar processors to execute multiple instructions simultaneously?
Static scheduling
Reduced complexity in design
Single instruction pipelines
Instruction-level parallelism (ILP)
Which feature allows superscalar processors to handle more tasks?
Single instruction pipelines
Simplified control flow
Multiple instruction pipelines
Limited hardware scheduling
What is the role of smart scheduling systems in superscalar processors?
To simplify instruction dependencies
To analyze and resolve instruction dependencies for efficient execution
To increase hardware complexity without improving performance
To reduce parallelism in instruction Execution
What is the purpose of register renaming in superscalar processors?
To eliminate control hazards
To resolve false dependencies like Write-After-Write (WAW)
To simplify the hardware design
To reduce the need for branch Prediction
How does superscalar processing differ from super-pipelining?
Handles parallel instructions
Issues multiple instructions per cycle
Only uses static scheduling
Focuses on dependencies
What is Out-of-Order Execution?
Executing in program order
Executing independently of program order
Avoiding parallelism
Disabling resources
Which dependency is associated with Read-After-Write (RAW) hazards?
True data dependency
Anti-dependency
Output dependency
Resource conflict
What is an example of a resource conflict in superscalar processors?
A procedural branch misprediction
Two instructions requiring the same Arithmetic Logic Unit (ALU)
An instruction waiting for a register to be read
False dependencies due to multiple pipeline registers
Which branch prediction technique uses historical behavior for accuracy?
Static branch prediction
Delayed branching
Dynamic branch prediction
Sequential execution
Which of the following best defines data parallelism?
Performing different operations on the same dataset simultaneously
Applying the same operation to multiple pieces of data simultaneously.
Executing multiple instruction streams on a single data stream
Dividing a single task among multiple processors for independent execution.
Which modern system is most commonly associated with leveraging data parallelism?
Central Processing Units (CPUs)
Graphics Processing Units (GPUs)
Distributed Databases
Cache Memory Systems
Which of the following parallelism classes does Hybrid Parallelism explicitly incorporate?
I. Data Parallelism
II. Bit-Level Parallelism
III. Instruction Level Parallelism
IV. Task Parallelism
I and III
III and II
IV and I
II and IV
Which of the following is an example of an architecture that utilizes hybrid parallelism?
CPU+GPU Systems
Accelerators in HPCs
Shared Memory Systems with Multicore CPUs
Real-time 3D Rendering
What is the primary goal of increasing bit-level parallelism in processors?
To reduce the number of instructions required for larger data operations
To simplify software development
To enhance instruction-level parallelism
To decrease memory size requirements
Which of the following advancements marked the first bit-parallel system?
Introduction of 4-bit processors in the 1970s
Development of VLSI technology
Release of the 16-bit Whirlwind computer in 1951
Launch of 64-bit systems like the Nintendo 64
Determine which is a key benefit of Instruction Level Parallelism (ILP).
Increases throughput by running multiple instructions in each clock cycle
Increases Hardware complexity
Promotes Scalability
Decreases hardware utilization
It is a technique of Instruction Level Parallelism that divides execution of instructions into several phases.
Out-of-order execution
Pipelining
Superscalar
Dynamic Instruction Scheduling
What is task parallelism?
Applying the same operation to different data subsets
Executing distinct tasks concurrently on multiple processors
Eliminating communication between tasks
Running sequential operations on one processor
Which is an example of task parallelism?
Filtering a dataset in parallel
Concurrently handling AI, physics, and rendering in a game
Summing elements of an array across cores
Encoding video frames simultaneously
