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WorksheetsCEA201
Total questions: 137
Worksheet time: 1hrs 9mins
How many bytes of data does each sector in the Winchester hard drive disk have?
128 bytes
256 bytes
512 bytes
1024 bytes
4096 bytes
A byte addressable microprocessor has 24 bit address. What is maximum memory capacity
4 MegaByte
8 MegaByte
16 MegaByte
32 MegaByte
What is the maximum addressable memory of a 32-bit microprcessor with 24-bit address
16GB
16MB
16 Gbits
16 Mbits
Consider a 5-drive, 200 GBytes-per-drive RAID array. What is the availabale data storage capacity for each of the RAID levels 5
200 GBytes
400 GBytes
600 GBytes
800 GBytes
None of the mentioned
Consider a 5-drive, 100 GBytes-per-drive RAID arrat. What is the acailable data storage capacity for each of the RAID levels 5?
400 GBytes
200 GBytes
300 GBytes
500 GBytes
In the direct mapping method from 256MB main memory with 512KB cache, what is the number of bits for the TAG element in the address?
6
7
8
9
In error correcting code (single ECC), how many bits are used to correct one bit in 8-bit data?
4
5
6
7
Consider an expression: NOT (1111 1010)
What is the result of this expression?
0000 1010
0000 0101
1111 0101
1111 1010
What is result of 10100101 XOR 11001001
11101101
10000001
01101100
10101100
(R1) = 01110110, (R2) = 11011111, the result of (R1) XOR (R2) is:
11011011
00010110
10101001
11001101
What is result left rotate of 10110101 by 2 bit?
01101011
10101101
01101101
11010110
11010100
What is the output of Left Shift Operator << on (00011000<<2)?
0110000
11000000
00000110
00000011
Express an integer number +18 (using 8-bits length) in twos complement representation.
00010010
10010010
00001101
10011101
Using Hamming Code with one error corection to store an 12-bit word in memory, the stored word 111001001101 consists of 8 bits data and 4 bit bits parity check. What are the parity bits?
0110
0111
1110
0101
None of the mentioned
1,1,1,0
1,1,1,1
1,0,1,0
0,1,1,0
None of the mentioned
What is the output of a NOT gate when the input is 0?
0
1
Undefined
2
When both inputs are 0, what is the result of a NOR gate?
0
1
2
Undefined
#NA
When both inputs are 1, what is the result of a NAND gate?
0
1
2
Undefined
#NA
A set-asociative cache consist of 64 lines, divided into four-line sets. 2^19-words main memory contains 4K blocks of 128 words each. How many bits are there in the tag field of the cache?
5
6
7
8
9
Consider a machine with a byte addressable main memory of 2^16 bytes and block size of 8 bytes. Assume that a direct mapped cache consisting of 32 lines is used with this machine. How many bits are there in the line field of the cache?
3
4
5
6
7
The instruction, which adds 1 to thevalue in a memory location, has five stages: fetch opcode (four cycles), fetch operand address (three cycles), fetch operand (three cycles), add 1 to operand (three cycles), and store operand (three cycles). An interrupt sends request at beginning of fetch operand stage. How many cycles does the processor enter the interrupt processing cycle?
6
7
8
9
10
In the concept of Register Windows, how many register groups are there?
4
3
2
No distinction
How many common classifications of parallel systems are there as proposed by Flynn?
2
3
4
5
If you have a boolean function with 3 variables, how many rows are there in the truth table?
8 rows
3 rows
6 rows
12 rows
Follow the Amdahl's law for multiprocessors, if only 10% of the code is inherently serial (f = 0.9), running the program on a multicore system with 4 processors, a performance gain (speedup factor) would be ____.
307%
297%
317%
327%
MIPS rate = 285.7
MIPS rate = 275.7
MIPS rate = 265.7
MIPS rate 295.7
Regarding the ALU(Arithmetic Logic Unit), besides basic arithmetic operations, what operations can it perform? (choose two correct answers)
It handles logical operations such as AND, OR, XOR, NOT.
It handles data transfer operations like MOVE, GO, JUMP.
It handles decoding operations after an instruction is fetched.
It handles bit shifting operations like multi and div operations by powers of two.
COUNTY
Why is cache design used in high-performance computing (HPC)? (Choose three correct answers)
Because there is a significant speed gap between the processor and the internal memory in HPC.
Because applications in HPC often require a large bandwidth to support intensive data proce
Because power consumption can be a significant operational cost in HPC environments.
Because multiple processors are often working in parallel, caches provide a way to efficiently manage data required by these processors
In the computer, what categories do external devices include? (choose 3 correct answers)
Human readable
Communic
Data Conversion
Machine readable
___ is a set of physical disk drives viewed by the operating system as a single logical drive.
CLV
SSD
RAID
CAV
refers to the operational units and their interconnections that realize the architectural
specifications.
Computer architecture
Computer function
Computer organization
Instruction set architecture
___ interprets the instructions in memory and causes them to be executed.
Registers
CPU interconnection
Arithmetic and Logic Unit (ALU)
I/O Modules
Control Unit (CU)
____ : If the operation involves reference to an operand in memory or available via I/O, then
determine the address of the operand.
Operand fetch
Data operation
Operand store
Operand address calculation
____ : Determine the address of the next instruction to be executed. Usually, this involves adding a fixed number to the address of the previous instruction.
Instruction fetch
Instruction operation decoding
Instruction address calculation
Operand fetch
Operand address calculation
_____ is (are) determined by the number of instructions that can be fetched and executed at the same time (the number of parallel pipelines) and by the speed and sophistication of the mechanisms that the processor uses to find independent instructions.
Instruction-level parallelism
Machine parallelism
Both instruction-level parallelism and machine parallelism
None of the mentioned
Consider the expression: NOT(A + B) = ? Apply DeMorgan's Theorem to replace at "?"
NOT A AND NOT B
NOT A OR NOT B
NOT A AND B
NOT A AND B
AND
OR
NAND
NOR
The operation ____ yields true (binary value 1) if and only if both of its operands are true.
OR
AND
XOR
NAND
The effective address of ____ is
EA = A + (R)
(R) (R) + 1
relative addressing
autoindexing
postindexing
preindexing
The effective address of Register indirect addressing mode is _____
EA = R
EA = (R)
EA = (R)+A
EA = (R)+(A)
Which of the following PDP series computers is known for its use of 12-bit instructions and a single general-purpose register, the accumulator?
PDP-8
PDP-10
PDP-11
PDP-6
Which RAID level uses striping technique with a minimum of 3 disks and provides fault tolerance through the use of parity bit?
RAID 0
RAID 1
RAID 2
RAID 3
Which register is the memory address register?
MAR
MBR
IR
PC
Which registers can interact with the secondary storage?
MAR
PC
IR
R0
All of the mentioned
For reads to and writes from main memory, ____ address in main memory. translates each virtual address into a physical address in main memory.
MAR
MMU
Overlays
TLB
Accumulator
Consider an expression: A + (B.C)
What expression is equal to the given expression?
(A + B). (A + C)
(A+B).C
A.(B+C)
NOT (A.(B+C))
In MASM32, which command is incorrect?
ADD EAX, a
ADD EAX, EBX
ADD a, EAX
ADD a, b
Consider some computer generations
1: the first computer generation
2: the second computer generation
3: the third computer generation
And some technologies are used in computer generations
A: Vacuum Tubes
B: Transistors
C: Integrated Circuits (IC)
D: Microprocessors
Select the main technology applied in each computer generation
1-D;2-C;3-B
1-A;2-C;3-D
1-A;2-B;3-C
1-D;2-B;3-C
What is the initial state of a process when it is admitted by the high-level scheduler, but not yet ready to execute?
New
Ready
Running
Halted
What electronic component is used to govern operations such as fetching, decoding, and performing arithmetic operations executed by a processor?
A. Using a system clock
B. Using a quartz crystal
C. Using a analog to digital converter
D. Using a counter
What is the most common mapping technique used in cache memory in modern compu
A. Direct Mapping
B. Fully Associative
C. Set Associative
D. None of the mentioned
What is the cache memory level that is integrated into the processor chip and has the lowest latency?
A. L1 cache
B. L2 cache
C. L3 cache
D. L4 cache
Which cache is not a shared cache?
A. L4 cache
B. L3 cache
C. L2 cache
D. L1 cache
Which of the following component does not belong to central processing unit?
A. System interconnection
B. Arithmetic and logic unit
C. Registers
D. Control unit
E. CPU interconnection
Which addressing mode allows direct specification of the memory address within the instruction?
A. Direct
B. Indirect
C. Register Indirect
D. Displacement
Which memory has the fastest speed and smallest capacity?
A. Cache
B. Main memory
C. HDD
D. Magnetic Disk
Which of the following memory devices has the lowest access speed?
A. ROMA
B. Flash memory
C. Magnetic tape
D. HDD
E. Cache
Which write technique in which all write operations are made to main memory as well as to the cache, ensuring that main memory is always valid.
A. Write through
B. Write back
C. Write around
D. No write allocate
Which one of four basic functions of computer describes the following statement?
"The paths among components are used to move data from memory to memory and from memory through gates to memory".
A. Data storage
B. Data processing
C. Data movement
D. Control
Which registers can be assigned to a variety of functions by the programmer?
A. Data registers
B. General purpose registers
C. Address registers
D. Condition codes (flags)
Which representation is most efficient to perform arithmetic operations on the signed integer numbers?
A. Sign-magnitude
B. 2's complement
C. 1's & 2's compliment
D. 1's complement
Which state indicates that a process is currently being executed by the processor?
A. Running
B. Ready
C. NewBorn
D. Halted
Which is the correct choice for the decription: "A single machine instruction controls the simultaneous execution of a number of processing elements such as vector and array processors"?
A. Single instruction, single data (SISD)
B. Single instruction, multiple data (SIMD)
C. Multiple instruction, single data (MISD)
D. Multiple instruction, multiple data (MIMD)
Which of the following components was used in the first ENIAC computer?
A. Bipolar transistors
B. Field transistors
C. Vacuum tubes
D. Semiconductor Ics
Which of the following components of CPU is responsible to direct the system to execute instructions?
A. Arithmetic and Logic Unit (ALU)
B. Control Unit (CU)
C. Registers
D. Random Access Memory (RAM)
Which component defines the system call interface to the operating system and facilitates binary portability?
A. Application Binary Interface
B. Application Programming Interface
C. Instruction Set Architecture
D. Central Processing Unit
(1) An I/O module must recognize one unique address for each peripheral it controls.
(2) I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on mainframes.
The statement (1) ___ is and (2) ____ is
A. true, false
B. true, true
C. false, true
D. false, false
Central processing unit (CPU) of IAS computer consists of ____
A. Main memory and ALU (arithmetic and logic unit)
B. ALU (Arithmetic and Logic Unit) and CU (Control Unit)
C. CU (Control Unit) and IO Module
D. ALU (Arithmetic and Logic Unit) and IO Module
For interrupts, all I/O modules share a common interrupt request line. When the processor senses an interrupt, it sends out an interrupt acknowledge. This signal propagates through a series of I/O modules until it gets to a requesting module. Which kind of interrupt technique is it?
A. Multiple interrupt lines
B. Software poll
C. Daisy chain
D. Bus arbitration
In isolated I/O, _____
A. The I/O devices and the memory share the same address space
B. The I/O devices have a separate address space from memory
C. The memory and I/O devices have an associated address space
D. A part of the memory is specifically set aside for the I/O operation
E. None of the mentioned
In MASM32, which OPCODE is used to compare two values?
A. WITH
B. CMP
C. IF... ELSE
D. TEST
"Multiple processors share a single memory or pool of memory by means of a shared bus or other interconnection mechanism; a distinguishing feature is that the memory access time to any region of memo is approximately the same for each processor". Which concept does the statement belong to?
A. Symmetric multiprocessor (SMP)
B. Nonuniform memory access (NUMA)
C. Cluster
D. Single instruction, multiple data (SIMD)
The pulse rate in the ck system is known as the
A. ck cycle
B. ck speed
C. ck time
D. ck tick
The first generation of computers used for digital logic elements and memory?
A. Transistor
B. Integrated Circuits
C. Large-scale integration
D. Vacuum Tubes
The task of subdivision is carried out dynamically by the OS and is known as ?
A. Scheduling
B. Memory management
C. Virtual Memory
D. All of the mentioned
The PC, IR, MAR, MBR registers belong to which of the following groups?
A. Control and Status Registers
B. User-Visible Registers
C. General Registers
D. Handle Registers
To enhance performance in a superscalar processor, which method(s) should we apply?
A. Duplication of resources.
B. Out-of-order issue.
C. Renaming registers
D. All of the mentioned.
The hardware mechanism that allows a device to notify the CPU is called ______
A. polling
B. interrupt
C. driver
D. controlling
The chunks of a program, known as pages, could be assigned to available chunks of memory, known as frames, is called _______
A. Swapping
B. Partitioning
C. Paging
D. Virtual Memory
E. Segmentation
With the hard disk data layout, the set of all the tracks in the same relative position on the platter, is called _______
A. Cylinder
B. Tracks
C. Inter-track gap
D. Sector
We have a long-term queue of process requests, typically stored on ______
A. main memory
B. disk
C. cache memory
D. registers
What is the correct order of memory access speed from fastest to slowest?
A. Registers > Cache > RAM > SSD
B. Cache > Registers > RAM > SSD
C. Registers > Cache > SSD > RAM
D. Cache > Registers > SSD > RAM
E. All of the mentioned are wrong
Sort the following memory types in ascending order by access speed:
A. HDD -Main Memory - L2 cache - L1 cache
B. HDD - Main Memory - L1 cache - L2 cache
C. HDD - L2 cache - L1 cache - Main Memory
D. Main Memory - L2 cache - L1 cache - HDD
What is correct about increasing performance and endurance?
A. Hard Disk- DRAM - NAND Flash - SRAM
B. Hard Disk - NAND Flash - DRAM SRAM
C. NAND Flash - Hard Disk - SRAM - DRAM
D. Hard Disk - DRAM - SRAM - NAND Flash
The speed of data delivery is your main concern when configuring a RAID drive for a Media Streaming Server. This server has two hard disks installed. What type of RAID should you install, and what type of data will be stored on Disk 1 and Disk 2?
A. RAID 0 - Disk 1 (Stripe) and Disk 2 (Stripe)
B. RAID 0 - Disk 1 (Mirror) and Disk 2 (Mirror)
C. RAID 1-Disk 1 (Stripe) and Disk 2 (Stripe)
D. RAID 1 - Disk 1 (Mirror) and Disk 2 (Mirror)
Which is the correct choice for sorting in increasing speed average of memory?
A. SSD Main Memory Cache Memory Magnetic Tape
B. Magnetic Tape SSD Cache Memory Main Memory
C. Magnetic Disk SSD Cache Memory Main Memory
D. Magnetic Disk Magnetic Tape Main Memory Cache Memory
FORU E. Magnetic Disk SSD Main Memory Cache Memory
A. SSD Main Memory Cache Memory Magnetic Tape
B. Magnetic Tape SSD Cache Memory Main Memory
C. Magnetic Disk SSD Cache Memory Main Memory
D. Magnetic Disk Magnetic Tape Main Memory Cache Memory
]E. Magnetic Disk SSD Main Memory Cache Memory
What are the most important general categories of data that machine instructions operate on?
A. Addresses, numbers, characters, and logical data
B. Text, images, and audio
C. Variables, functions, and arrays
D. Instructions, control signals, and registers
The basic components of a computer are:
A. Main memory, CPU, I/O modules and system interconnection
B. Main memory, CPU, I/O modules and Storage device
C. Main Memory, CPU, Peripherals and Storage device
D. Main memory, CPU, I/O modules and Storage device
What does CISC stand for?
A. Complex Instruction Set Computer
B. Computer Instruction Set Complex
C. Complex Instruction Summarize Computer
D. Computer Instruction Summarize Complex
What is the primary purpose of the "Fetch instruction" phase in the operation of a processor?
A. To read an instruction from memory
B. To interpret the instruction
C. To perform arithmetic operations on data
D. To write data to memory
What is the main difference between x86 and ARM instruction formats?
A. x86 instructions are variable in length, while ARM instructions are fixed
B. x86 instructions are fixed in length, while ARM instructions are variable
C. Both x86 and ARM instructions are fixed in length
D. Both x86 and ARM instructions are variable in length
What is the benefit of using a superscalar organization over a scalar organization?
A. It increases the instruction throughput and improves the performance
B. It reduces the power consumption and the heat dissipation
C. It simplifies the instruction set and the compiler design
D. All of the mentioned
E. None of the mentioned
What are the key differences in the architecture of NOR and NAND flash memory?
A. NOR flash memory cells are connected in series, while NAND flash memory cells are connected in parallel
B. NOR flash memory cells are connected in parallel, while NAND flash memory cells are connected in series
C. Both NOR and NAND flash memory cells are connected in series
D. Both NOR and NAND flash memory cells are connected in parallel
E. All of the mentioned are wrong
What is the main benefit of using ARM processors over other processors?
A. Low cost and low power consumption
B. Higher degree of multi-tasking
C. Lower error or glitches
D. Efficient memory management
What is an interrupt vector?
A. Part of memory which contains the addresses of interrupt handlers
B. A signal an I/O device sends to CPU
C. A signal an I/O software sends to CPU
D. None of the mentioned
What does the term "instruction-level parallelism" refer to in computer architecture?
A. The degree to which instructions in a program can be executed in parallel
B. The number of processor cores in a multi-core CPU with multiple resources
C. The complexity of the instruction set architecture
D. The length of an instruction cycle with high level programing language
What is one of the advantages of using a register file in computer architecture?
A. Reduction in memory accesses, saving time
B. More efficient use of space due to dynamic adaptation
C. Efficient handling of both local and global variables
D. Easier management of cache residency
What is the special feature of Memory Cache?
A. Allows faster access than DRAM memory
B. Memory cache is outboard storage memory
C. Allows faster access than CPU registers
D. Fixed memory - Read Only Memory
E. Has a larger capacity than HDD
What role does an Application Programming Interface (API) play in software development?
A. It allows program access to hardware resources using high-level language libraries
B. It defines low-level machine instructions
C. It provides a standard for binary portability
D. It manages system resources for the operating system and machine language instructions
What is the most important function of the control unit (CU)?
A. It manages the order of running instructions.
B. It will read and process data from main memory.
C. It directs the operation of the other CPU components.
D. It will read instructions from main memory then decoding them.
What is the most important characteristic of the Synchronous Bus?
A. Data is transmitted at the same time
B. The occurrence of one event on a bus follows and depends on the occurrence of a previous event.
C. The occurrence of events on the bus is determined by a clock
D. No common clock signal controlling operation
What is one advantage of Nonuniform Memory Access (NUMA) over Uniform Memory Access (UMA)?
A. NUMA provides each processor with its own local memory, reducing memory access times
B. NUMA allows all processors to access the same memory location simultaneously
C. NUMA is easier to implement than UMA
D. NUMA provides limited memory capacity
What is the main distinction between Interrupt-Driven I/O and Direct Memory Access (DMA)?
A. Interrupt-Driven I/O involves the CPU in every data transfer, while DMA bypasses the CPU and transfers data directly between I/O device and memory
B. Interrupt-Driven I/O requires special hardware and software support, while DMA does not need any additional components
C. Interrupt-Driven I/O is suitable for small and frequent data transfers, while DMA is suitable for large and infrequent data transfers
D. All of the mentioned
What is Memory Address Register (MAR)?
A. Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit.
B. Employed to hold temporarily the righthand instruction from a word in memory.
C. Contains the address in memory of the word to be written from or read into the MBR.
D. Contains the address of the next instruction pair to be fetched from memory.
What is true about IAS Memory Formats?
A. The memory of the IAS consists of 1000 storage locations (called words) of 32 bits each
B. Only data is stored in the memory
C. Both data and instructions are stored in the memory
D. Only instructions are stored in the memory
What is false about the von Neumann architecture?
A. Data and instructions are stored in a single read-write memory.
B. The contents of this memory are addressable by location, without regard to the type of data contained there.
C. Execution occurs in a sequential fashion (unless explicitly modified) from one instruction to the next.
D. Data is stored in main memory and instructions are stored in cache memory
What is the significance of the program counter (PC) in the fetch phase of the instruction cycle?
A. The program counter (PC) is not used in the fetch phase, and its role is limited to tracking the number of instructions executed by the CPU
B. The program counter (PC) in the fetch phase holds the memory address of the next instruction to be fetched and executed
C. The program counter (PC) is responsible for executing instructions and has no specific role during the fetch phase
D. The program counter (PC) is only relevant in multi-core processors and does not contribute to the fetch n multi-core proce phase of the instruction cycle in single-core systems
What is the distinction between Computer Architecture and Computer Organization?
A. Computer Architecture is the way the system is structured, while Computer Organization is those attributes of a system that are visible to the user
B. Computer Architecture is those attributes of a system that are visible to the user, while Computer Organization is the way the system is structured
C. Computer Architecture and Computer Organization are the same
D. Computer Architecture is slower than Computer Organization
What is incorrect about SSDs have the following advantages over HDDs?
A. Higher access times and latency rates: Over 10 times slower than the HDD.
B. Durability: Less susceptible to physical shock and vibration.
C. Longer lifespan: SSDs are not susceptible to mechanical wear.
D. Lower power consumption: SSDs use considerably less power than comparable-size HDDs.
E. Quieter and cooler running capabilities: Less space required, lower energy costs, and a greener enterprise.
What is the primary function of the Arithmetic and Logic Unit (ALU) in a processor?
A. Perform actual computations and data processing
B. Control the movement of data and instructions
C. Act as an interface to the system bus
D. Manage the internal processor memory
What is the role of the registers in a processor?
A. Registers in a processor provide fast, temporary storage for data and instructions, facilitating efficient access during instruction execution
B. Registers are only used to store data temporarily during the execution of a program and do not contribute to the processing of instructions
C. Registers are solely responsible for storing data from the main memory and have no involvement in holding instructions or facilitating data manipulation
D. Registers are only necessary when the CPU is idle and have no impact on the speed or efficiency of instruction execution
What is the role of the control unit in a processor?
A. The control unit's primary role is to perform arithmetic and logical operations within the processor, orchestrating the manipulation of data
B. The control unit only manages the flow of data between the CPU and external devices and does not play a significant role in executing instructions
C. The control unit is solely responsible for managing the flow of instructions from secondary storage to RAM and does not have a role in the internal operation of the CPU
D. The control unit in a processor directs and coordinates the execution of instructions, interpreting and managing the flow of operations within the CPU
What is the main benefit of using RISC over CISC?
A. RISC has more instructions and addressing modes than CISC
B. RISC has faster instruction execution and simpler instruction decoding than CISC
C. RISC has variable-length instruction formats and direct memory access than CISC
D. RISC has more registers and pipelines than CISC
What is the main idea of using Hamming code for error correction?
A. Adding extra parity bits to the data bits such that the number of 1s in each subset of bits is even
B. Adding extra parity bits to the data bits such that the number of 1s in each subset of bits is odd
C. Adding extra parity bits to the data bits such that the parity bits form a binary number indicating the position of the error bit
D. Adding extra parity bits to the data bits such that the parity bits form a binary number indicating the number of error bits
What is the function of the bus system in the computer?
A. Extend the communication function of the computer
B. Connect components in the computer
C. Control peripherals
D. Transform signals in the computer
E. All of the mentioned
Which of the following statements is incorrect about Translation Look-aside Buffer (TLB)?
A. The use of TLB eliminates the need for keeping a page table in memory
B. TLB only maintains a subset of the entries stored in the full memory-based page table
C. When there is a TLB miss the system needs to access the page table
D. A translation lookaside buffer (TLB) is a memory cache that stores the recent translations of virtual memory to physical memory
Which statement is incorrect about RISC and CISC architecture?
A. CISC architecture is more convenient for programmers than RISC architecture.
B. CISC architecture has more operands in a instruction compared to RISC architecture.
C. CISC architecture has a more flexible instruction set than RISC architecture.
D. CISC architecture requires more general-purpose registers than RISC architecture.
Which of the following statement is correct in the context of Instruction Pipelining?
A. Instruction Pipelining reduces the efficiency of instruction execution by introducing delays and dependencies between instructions
B. Instruction Pipelining is only effective for specific types of instructions and has no impact on the overall efficiency of instruction execution
C. Instruction Pipelining enhances efficiency by enabling simultaneous execution of multiple instructions in different stages, boosting overall throughput
D. Instruction Pipelining improves efficiency by processing multiple instructions simultaneously, reducing execution time. However, it can face challenges like hazards, introducing delays and impacting overall performance
Which of the following statements is part of the Von Newmann principle?
A. The computer uses a program counter to indicate the location of the next statement
B. Computer can control all operations with a single program
C. Computer memory is not addressable
D. Each instruction must have a memory area containing the address of the next instruction
Which of the following statements is NOT part of the Von Newmann principle?
A. Computers can operate according to a stored program
B. The computer uses a program counter to indicate the location of the next statement
C. A computer's memory is addressable
D. Each statement must have a memory area containing the address of the next instruction
Which of the following statements is true for Von Neumann architecture?
A. Shared bus between the program memory and data memory
B. Separate bus between the program memory and data memory
C. External bus for program memory and data memory
D. External bus for data memory onlyo
Which one of the following is an invalid about RAM?
A. Both static and dynamic RAMs are volatile; that is, power must be continuously supplied to the memory to preserve the bit values.
B. A dynamic memory cell is simpler and smaller than a static memory cell.
C. Both static and dynamic RAMs requires the supporting refresh circuitry
D. SRAMs are somewhat faster than DRAMS
Which of the following determines the Bus Width?
A. The clock speed of the CPU
B. The number of cores in the processor
C. The size of the motherboard
D. The number of parallel lines in the data bus
E. Number of components connected to Bus
Which of the following statement is correct about addressing modes?
A. They define how the operands of an instruction are specified, including immediate, register, direct, and indirect addressing modes
B. Addressing modes are irrelevant in computer architecture, and all instructions only operate on values stored in registers
C. Addressing modes are limited to only immediate and direct modes; register and indirect addressing modes are not used in modern computer systems
D. All instructions in computer architecture use indirect addressing modes, making it the only relevant mode for operand specification
When considering the number of pipeline stages, what trade-offs must be made in computer architecture?
A. Trade-offs between potential speedup and increased cost and delays
B. Trade-offs between software and hardware
C. Trade-offs between speed and efficiency
D. Trade-offs between branching and executing instructions with conditions
Why is it essential to use symbolic representation of machine instructions?
A. It makes machine instructions more human-readable and understandable
B. It reduces the overall complexity of computer systems and user programs
C. It minimizes the need for memory storage for the user programs
D. It enables fastest execution of high level language instructions
How does Boolean algebra contribute to the design of digital circuits?
A. It simplifies the implementation of desired functions
B. It helps in the analysis of economic data
C. It facilitates the design of analog circuits
D. It is primarily used for chemical engineering and physical engineering
How does pipelining in a RISC architecture handle branch instruction?
A. By using NOOP instructions inserted by the compiler or assembler
B. By eliminating branch instructions from the instruction stream
C. By executing branch instructions in a separate pipeline
D. By delaying all instructions until branch instructions are executed
How do data registers and address registers differ in some computer systems?
A. Address registers can be employed in calculating operand addresses, while data registers hold data.
B. Data registers are only used for stack-related operations
C. Data registers are used for indexed addressing, while address registers are used for data storage
D. Address registers are reserved for segmented addressing, while data registers are general-purpose
How does multithreading improve the performance of a processor?
A. It increases the instruction-level parallelism by issuing multiple instructions from different threads in the same cycle
B. It increases the thread-level parallelism by executing multiple threads on different cores or processors
C. It increases the utilization of the processor resources by hiding the latency of long-latency events such as cache misses or branch mispredictions
D. All of the mentioned
Choose the most four basic functions of a computer.
A. Moving data, storing data, processing data, controlling.
B. Supporting operating system, accessing hard disks, supporting network connections, supporting HDMI ports.
C. Reading disks, accessing network resources.
D. Reading data from keyboard, printing data to monitor, allowing network connections.
Control and status registers are used by which entities to control the operation of the processor?
A. Privileged, operating system programs
B. Machine or assembly language programmers
C. External I/O devices
D. Main memory modules
Central processing unit (CPU) of IAS computer consists of ____
A. Main memory and ALU (arithmetic and logic unit)
B. ALU (Arithmetic and Logic Unit) and CU (Control Unit)
C. CU (Control Unit) and IO Module
D. ALU (Arithmetic and Logic Unit) and IO Module
During the development process of the computer, which of the following statements is false?
A. The second generation uses transistors
B. The first generation uses vacuum tubes
C. The fourth generation uses integrated circuit
D. The third generation uses transistor
In the CPU, what is the functionality of the control unit?
A. To decode program instructions
B. To controls the sequence of operations
C. To store program instructions
D. To transfer data to primary storage
In terms of performance, what is the main advantage of a solid state drive over a magnetic disk?
A. A solid state drive has faster access time, lower latency, and higher reliability
B. A solid state drive has larger capacity, lower power consumption, and lower cost
C. A solid state drive has better compatibility, longer lifespan, and higher security
D. A solid state drive has none of the mentioned advantages over a magnetic disk
In SuperScalar computer architecture, the primary goal of utilizing multiple processors concurrently is to
A. Increase processing speed by increasing CPU frequency.
B. Improve performance by executing more than one instruction per machine cycle.
C. Reduce the size of the CPU to conserve energy.
D. Enhance computational power by increasing the number of CPU cores.
