WorksheetsSystemVerilog Quiz
Total questions: 8
Worksheet time: 17mins
Which of the following is a correct way to declare an enum in SystemVerilog?
enum {IDLE, RUN, STOP} mode;
enum int {IDLE, RUN, STOP};
typedef enum {IDLE, RUN, STOP} mode_t; mode_t mode;
enum = {IDLE, RUN, STOP} mode;
What will be the default integer value assigned to the first member of an enum if not explicitly defined?
-1
0
1
Undefined
Consider the following enum: typedef enum int {RED = 2, GREEN, BLUE} color_t; What is the value of BLUE?
2
3
4
It will cause an error
Coefficient of autonomous LFSR is c[4:1] = 1001. What is the output after 3rd clock cycle if initial data is 0001?
For the following code segment, What is the final value of variable "c" integer a, b, c; initial begin a = 55; b = 10; c = 5; a = b * c; b = a - 25; c = a + b; end
For the following code segment indicate, Raising edges of the clock will appear at times ____,_____, ____,______.
If the 8-bit variable "data" declared as "reg [7:0] data" is initialized to 8'b10011001, what will be its value after execution of the following code segment? always @(posedge clock) begin data =data >>>1; data[0] = data[7]; end
In the given code, statement 2 will executed at
initial begin
#5 x = 1'b0; // statement 1
#15 y = 1'b1; // statement 2
end
