WorksheetsComputer Systems Architecture
Total questions: 94
Worksheet time: 48mins
It is a communication pathway that connects two (2) or more devices or modules used for transferring data.
Computer Bus
Data Bus
Address Bus
Control Buss
What consists of a set of conductors such as ribbon cables, external cabling, copper tracks on a printed circuit board, microscopic aluminum trails on the surface of a silicon chip, and many other forms?
Computer Bus
Data Bus
Address Bus
Control Buss
What allows each device connected, in the form of trailings or wires, to transmit a bit of data (1 or 0), making the collection of wires capable of transferring a byte or a word at a time depending on its width?
Computer Bus
Data Bus
Address Bus
Control Buss
In reality, each bus consists of how many distinct physical lines divided into three (3) subassemblies?
50 to 100 distinct physical lines
1 to 50 distinct physical lines
1 to 500 distinct physical lines
100 to 150 distinct physical lines
Also known as Memory Bus
System Bus
Address Bus
Data Bus
Control Bus
Also known as Command Bus
System Bus
Address Bus
Data Bus
Control Bus
What is the unidirectional bus that transports memory addresses which the processor wants to access to read or write data?
System Bus
Address Bus
Data Bus
Control Bus
What is the bidirectional bus that transfers instructions coming from or going to the processor?
System Bus
Address Bus
Data Bus
Control Bus
What is the bidirectional bus that transports orders and synchronization signals coming from the control unit and traveling to all other hardware components, and also transmits response signals from the hardware?
System Bus
Address Bus
Data Bus
Control Bus
Which data transmission method is normally used for long-distance data transfer and when the amount of data is relatively small?
Serial
Parallel
Singly
Doubly
Which data transmission method ensures data integrity by sending data bits one by one in a specific order?
Serial
Parallel
Singly
Doubly
In which transmission method are multiple data bits transmitted over multiple channels at the same time?
Serial
Parallel
Control Bus
Memory Bus
Data can be sent faster than using serial transmission methods.
Serial
Parallel
Control Bus
Memory Bus
In which type of bus protocol are data bits transmitted as a continuous stream synchronized with a master clock?
Wired
Wireless
Synchronous
Asynchronous
Which type of bus protocol does not use start bits, stop bits, and gaps?
Parallel
Serial
Synchronous
Asynchronous
Which protocol is highly dependent on correct timing synchronization between devices?
Parallel
Serial
Synchronous
Asynchronous
Which bus protocol uses start bits and stop bits to synchronize data transmission?
Parallel
Serial
Synchronous
Asynchronous
In which type of bus protocol can data bits be sent at any point in time?
Data Bus
Address Bus
Synchronous
Asynchronous
In asynchronous transmission, what is used to provide time between data transmissions?
Control Lines
Gaps
Clock Pulses
Address Signals
What does a bus transfer from one place to another?
Electrical signals
Magnetic fields
Sound waves
Radio signals
What travels between the CPU and memory along the data bus?
Clock signals
Data
Addresses
Instructions only
Characteristics of Computer Bus
All types of buses found in computer transfer data between computer peripherals
connected to it.
Data Sharing
Addressing
Power
Timing
Characteristics of Computer Bus
A bus has address lines that match those of the processor. This allows data to be sent to
or from specific memory locations.
Data Sharing
Addressing
Power
Timing
Characteristics of Computer Bus
A bus supplies power to various peripherals connected to it.
Data Sharing
Addressing
Power
Timing
Characteristics of Computer Bus
A bus provides a system clock signal to synchronize the peripherals attached to it with the
rest of the system.
Data Sharing
Addressing
Power
Timing
What is a component that routes data between a computer’s buses and enables all components to communicate with each other?
Processor
Motherboard
Chipset
Hard Drive
Which part of the chipset controls the transfer of data between the processor and RAM?
Southbridge
Internal Bus
Northbridge
Expansion Bus
Why is the Northbridge physically located near the processor?
To minimize power consumption
To reduce heat
To control data transfer between processor and RAM
To manage peripheral devices
This allows the processor to communicate with the system’s central memory or the RAM.
Internal Bus (Front-Side Bus or FSB)
Northbridge
Southbridge
Expansion Bus
Which part of the chipset handles communication between peripheral devices?
Northbridge
Front-Side Bus
Southbridge
Internal Bus
What is another term for the Southbridge?
Memory Hub
Expansion Bus
Input/Output Controller Hub (ICH)
Peripheral Manager
Which bus allows various motherboard components like USB or serial ports to communicate?
Address Bus
Expansion Bus
Control Bus
Data Bus
Another term for Northbridge?
Memory Controller
Front-Side Bus or FSB
Input/Output controller or expansion controller
Input/Output Bus
Another term for Internal Bus?
Memory Controller
Front-Side Bus or FSB
Input/Output controller or expansion controller
Input/Output Bus
Another term for Expansion Bus?
Memory Controller
Front-Side Bus or FSB
Input/Output controller or expansion controller
Input/Output Bus
Computer Bus Technologies --->>> Previously Used Technology
IBM introduced this bus for IBM PC using an 8088 microprocessor. This has an 8-bit data bus and 20 address lines at a clock speed of 8 MHz.
Industry Standard Architecture (ISA)
Video Electronics Standards Association (VESA)
Accelerated Graphics Port (AGP)
Peripheral Component Interconnect (PCI)
Computer Bus Technologies --->>> Previously Used Technology
This bus is a standard interface between a computer and its expansion. As applications became more graphically intensive, ________ was introduced to maximize throughput of video graphics memory. This also provides fast data flow between stations and can transfer up to 132 Mbps.
Industry Standard Architecture (ISA)
Video Electronics Standards Association (VESA)
Accelerated Graphics Port (AGP)
Peripheral Component Interconnect (PCI)
Computer Bus Technologies --->>> Previously Used Technology
This is connected to the CPU. This operates at the speed of the processor bus and implies that video information is sent quickly to the card for processing. The data transfer rate ranges from 264 Mbps to 528Mbps and 800 Mbps up to 1.5 Gbps. Identified by its brown color.
Industry Standard Architecture (ISA)
Video Electronics Standards Association (VESA)
Accelerated Graphics Port (AGP)
Peripheral Component Interconnect (PCI)
Computer Bus Technologies --->>> Previously Used Technology
Intel Corporation developed this bus. This includes a 32 or 64-bit bus that runs at 33/66 MHz clock speed. It offers many advantages for connections to hubs, routers, and network interface cards (NIC). In particular, provides more bandwidth up to 1 Gigabit per second as needed by these hardware components.
Industry Standard Architecture (ISA)
Video Electronics Standards Association (VESA)
Accelerated Graphics Port (AGP)
Peripheral Component Interconnect (PCI)
Computer Bus Technologies --->>> Currently Used Technology
It is a set of ANSI standard electronic interfaces that allows PCs to communicate faster with peripheral hardware (e. g., disk drives, tape drives, CD-ROM drives, printers, and scanners). It is more flexible than previous parallel data transfer interfaces.
Small Computer Systems Interface (SCSI)
Personal Computer Memory Card Industry Association (PCMCIA)
Peripheral Component Interconnect Express (PCIe)
Universal Serial Bus (USB)
Computer Bus Technologies --->>> Currently Used Technology
This was founded to give a standard bus for laptop computers. This card has a 68-pin connector that connects into a slot in the PC. These cards are plug-and-play devices that are often hot-swappable in most of the operating systems.
Small Computer Systems Interface (SCSI)
Personal Computer Memory Card Industry Association (PCMCIA)
Peripheral Component Interconnect Express (PCIe)
Universal Serial Bus (USB)
Computer Bus Technologies --->>> Currently Used Technology
It is an interface standard for connecting high-speed components. It comes in different physical configurations: x1, x4, x8, x16, x32. The number after the “x” implies the number of lanes (how data travels to) that it has.
Small Computer Systems Interface (SCSI)
Personal Computer Memory Card Industry Association (PCMCIA)
Peripheral Component Interconnect Express (PCIe)
Universal Serial Bus (USB)
Computer Bus Technologies --->>> Currently Used Technology
It connects peripheral devices such as digital cameras, mice, keyboards, printers, scanners, media devices, external hard drives, and flash drives. It is intended to enhance plug-and-play and to allow hot-swapping.
Small Computer Systems Interface (SCSI)
Personal Computer Memory Card Industry Association (PCMCIA)
Peripheral Component Interconnect Express (PCIe)
Universal Serial Bus (USB)
This allows user input from the outside world to the computer.
Input Peripherals
Output Peripherals
Input-Output Peripherals
Storage
This allows information output from the computer to the outside world.
Input Peripherals
Output Peripherals
Input-Output Peripherals
Storage
This allows information to be sent through input and output.
Input Peripherals
Output Peripherals
Input-Output Peripherals
Storage
This allows the usage of I/O for storing and fetching of information.
Input Peripherals
Output Peripherals
Input-Output Peripherals
Storage
I/O Characteristics
I/O devices are incredibly diverse with respect to the following:
Input, output, or storage purposes
Behavior
Partner
Data Rate
Control
I/O Characteristics
I/O devices are incredibly diverse with respect to the following:
Input, output, or storage purposes
Behavior
Partner
Data Rate
Control
I/O Characteristics
I/O devices are incredibly diverse with respect to the following:
Input, output, or storage purposes
Behavior
Partner
Data Rate
Control
I/O Characteristics
I/O devices are incredibly diverse with respect to the following:
Input, output, or storage purposes
Behavior
Partner
Data Rate
Control
I/O Characteristics
I/O devices are incredibly diverse with respect to the following:
Human or machine interaction
Behavior
Partner
Data Rate
Control
I/O Characteristics
I/O devices are incredibly diverse with respect to the following:
The amount of data transferred to or from the I/O device in a period. It is typically measured in bits per second
Behavior
Partner
Data Rate
Control
I/O Characteristics
I/O Considerations:
This refers to how fast the device is.
Performance
Expandability
Dependability
Cost
Size and Weight
I/O Characteristics
I/O Considerations:
This refers to the expansion of the I/O device.
Performance
Expandability
Dependability
Cost
Size and Weight
I/O Characteristics
I/O Considerations:
This refers to the capability of the range and control of an I/O device.
Performance
Expandability
Dependability
Cost
Size and Weight
I/O Characteristics
I/O Considerations:
This refers to the cost (how cheap or expensive) of an I/O module or device.
Performance
Expandability
Dependability
Cost
Size and Weight
I/O Characteristics
I/O Considerations:
These refer to the dimensions of an I/O device.
Performance
Expandability
Dependability
Cost
Size and Weight
I/O Performance
This is the amount of information that can be input (output) and communicated across an interconnect (say, for example, a bus) to the processor or memory (I/O device) per unit time.
I/O Performance
I/O Bandwitdth
I/O Response Time
I/O Data Transfer
I/O Performance
This is the total elapsed time to accomplish by an input or output operation. This is also an especially important performance metric in real-time systems.
I/O Performance
I/O Bandwitdth
I/O Response Time
I/O Data Transfer
I/O Performance
Also known as Throughput
I/O Performance
I/O Bandwitdth
I/O Response Time
I/O Data Transfer
I/O Performance
Also known as Latency
I/O Performance
I/O Bandwitdth
I/O Response Time
I/O Data Transfer
I/O Performance
Two questions in I/O Bandwidth
How much data can be moved through the system at a certain time?
How many I/O operations can be done per unit time?
How much memory is installed in the system?
How fast the processor can execute a single instruction?
Modes of I/O Transfer
These instructions are the result of I/O instructions written in a computer program. The instruction in the program initiates each data item transfer. Usually, the program controls data transfer to and from the CPU and peripheral. Transferring data requires constant monitoring of the peripherals by the CPU.
Programmed I/O
Interrupt Initiated I/O
Direct Memory Access (DMA)
Performance I/O
Modes of I/O Transfer --->>> Programmed I/O
For addressing the I/O device.
Address Registers
Data Registers
Control Registers
I/O Registers
Modes of I/O Transfer --->>> Programmed I/O
For holding I/O data.
Address Registers
Data Registers
Control Registers
I/O Registers
Modes of I/O Transfer
The interface determines when the peripheral is ready for data transfer, then it generates an interrupt. After receiving the interrupt signal, the CPU stops the task it processes and service the I/O transfer. Then, it returns to its previous processing task. It also require CPU immediate attention.
Programmed I/O
Interrupt Initiated I/O
Direct Memory Access (DMA)
Control I/O
Modes of I/O Transfer
It is a technique of removing the CPU from the path and letting the peripheral device manage the memory buses directly to improve the speed of transfer. It manages the transfer of data between peripherals and memory unit. CPU initiates the transfer, does other operations while the transfer is in progress, and receives an interrupt when the transfer has been completed.
Programmed I/O
Interrupt Initiated I/O
Direct Memory Access (DMA)
Control I/O
Modes of I/O Transfer --->>> Interrupt Initiated I/O --->>> Uses of Interrupts
This process periodically checks for external events (ex. checking keyboard input).
As an external event notifier.
As a completion signal.
As a means of allocating CPU time.
The interrupt as an abnormal event indicator.
Software interrupts.
Modes of I/O Transfer --->>> Interrupt Initiated I/O --->>> Uses of Interrupts
It can be a notifier when a process is complete.
As an external event notifier.
As a completion signal.
As a means of allocating CPU time.
The interrupt as an abnormal event indicator.
Software interrupts.
Modes of I/O Transfer --->>> Interrupt Initiated I/O --->>> Uses of Interrupts
The time between interrupt pulses is known as a quantum, which represents the time that each program or process will have allotted to it.
As an external event notifier.
As a completion signal.
As a means of allocating CPU time.
The interrupt as an abnormal event indicator.
Software interrupts.
Modes of I/O Transfer --->>> Interrupt Initiated I/O --->>> Uses of Interrupts
It uses traps or exceptions to avoid errors or illegal instructions.
As an external event notifier.
As a completion signal.
As a means of allocating CPU time.
The interrupt as an abnormal event indicator.
Software interrupts.
Modes of I/O Transfer --->>> Interrupt Initiated I/O --->>> Uses of Interrupts
Programs or applications with higher priority and privileges (depending on the user’s and system’s grant) can request a special interrupt if prompted.
As an external event notifier.
As a completion signal.
As a means of allocating CPU time.
The interrupt as an abnormal event indicator.
Software interrupts.
Modes of I/O Transfer --->>> Direct Memory Access --->>> Main Conditions
The following are the Main Conditions of DMA EXCEPT
Method to connect the I/O module and the memory
The I/O module must be able to read from and write to the memory
As a means of allocating CPU time.
Method to avoid conflict between the CPU and the I/O module writing to memory at the same
time.
Modes of I/O Transfer --->>> Direct Memory Access --->>> Methods of Execution
The two (2) methods of execution.
Buffer Chaining
Operation Chaning
Control Chaining
Address Chaining
Modes of I/O Transfer --->>> Direct Memory Access --->>> Methods of Execution
The following are characteristics of Buffer Chaining EXCEPT
It handles multiple transfers without the processor.
The device gives a linked list of buffers.
The device hardware uses the next buffer on the list automatically.
The device carries out successive commands automatically
Modes of I/O Transfer --->>> Direct Memory Access --->>> Methods of Execution
The following are characteristics of Operation Chaining EXCEPT
The processor gives a series of commands to the device, sometimes called a channel
program.
Further optimization for smart device
The device hardware uses the next buffer on the list automatically.
The device carries out successive commands automatically
I/O Controller --->>> Functions
It includes the connection, voltage supply, protocol enactor, clocking.
Interface translation
Addressing
Multiplexing
Buffering
Error detection and correction
I/O Controller --->>> Functions
It is able to process memory locations or addresses for the function of processing.
Interface translation
Addressing
Multiplexing
Buffering
Error detection and correction
I/O Controller --->>> Functions
It can combine multiple signals over the bus to reduce multiple bus usage.
Control of Multiple Steps
Addressing
Multiplexing
Buffering
Error detection and correction
I/O Controller --->>> Functions
It gives data transfer a boost by preloading data into memory before processing.
Control of Multiple Steps
Addressing
Multiplexing
Buffering
Error detection and correction
I/O Controller --->>> Functions
It can detect errors and correction.
Control of Multiple Steps
Addressing
Multiplexing
Buffering
Error detection and correction
I/O Controller --->>> Functions
This reduces CPU workload due to I/O controller being the one that processes I/O instructions.
Control of Multiple Steps
Addressing
Multiplexing
Buffering
Error detection and correction
Serves as an intermediary interface between the CPU and a specific device that accepts commands from the CPU and controls the exact device after.
I/O Controller
I/O Data Transfer
I/O Performance
I/O Characteristics
Serve as direct interfaces between a general system bus and each of the system’s peripheral devices. In
general, It simplify the task of interfacing peripheral devices to a CPU.
I/O Controller
I/O Data Transfer
I/O Performance
I/O Characteristics
They support DMA so the CPU may be free to perform other tasks.
I/O Controller
I/O Data Transfer
I/O Performance
I/O Characteristics
Allows the processing of each instruction to progress in parallel.
I/O Controller
I/O Data Transfer
I/O Performance
I/O Characteristics
A small piece of software that tells the operating system and other software how to communicate with a piece of hardware.
I/O Controller
I/O Data Transfer
I/O Performance
Device Driver
Provide the specialized circuitry required to interface different types of peripherals to the computer.
Device Controllers
Buffer Chaining
Operation Chaining
Data Rate
Which of the following statements about Parallel Bus are correct?
Statement 1: Parallel bus transmits several streams of data simultaneously along multiple channels.
Statement 2: Parallel bus is used mainly for long-distance communication.
Statement 3: Parallel bus operates in half-duplex mode — data is either sent or received.
Statement 4: Parallel bus requires fewer interconnecting cables and occupies less space.
Statements 1 and 3 only
Statements 1, 2, and 3
Statements 2 and 4 only
Statements 1, 3, and 4
Which of the following statements about Serial Bus are correct?
Statement 1: Serial bus can transmit fewer data in faster clock cycles to achieve a higher data rate.
Statement 2: Serial bus is half-duplex — sender can either send or receive but not both.
Statement 3: Serial bus requires fewer interconnecting cables and occupies less space.
Statement 4: Serial bus is used for long-distance communication.
Statements 1, 2, and 3 only
Statements 1, 3, and 4 only
Statements 2 and 3 only
Statements 1 and 4 only
What is the process called where multiple requests are recognized and priority is given to one of them?
Multiplexing
Arbitration
Serialization
Priority
Which of the following statements about Centralized Arbitration are correct?
Statement 1: In centralized arbitration, an arbitration circuit receives requests from the contending bus masters and then decides which of them is to be given control of the bus.
Statement 2: A single hardware device, known as a bus controller or arbiter, is responsible for allocating time to bus.
Statement 3: The device may be part of the CPU or a separate module such as daisy-chaining.
Statement 4: Each module may claim the bus independently.
Statements 1, 2, and 3 only
Statements 1 and 2 only
Statements 1, 2, and 4 only
All statements are correct
Which of the following statements about Distributed Arbitration are correct?
Statement 1: There is no central controller. Each module may claim the bus.
Statement 2: All devices monitor all the request lines.
Statement 3: In a system with distributed arbitration, each of the masters takes part in the arbitration process.
Statement 4: The system lacks a specific arbiter—each master monitors the other masters and decides whether to continue competing for the bus or give up and wait until later.
Statements 1 and 2 only
Statements 1, 2, and 4 only
Statements 1, 2, 3, and 4
Statements 2, 3, and 4 only
