Free Printable Circuitos Lógicos

1.

All numbering systems have the same basic composition and _____.

a)

base number

b)

decimal

c)

power

d)

function

2.

Which of the following number system has base of 10.

a)

$297_{10}$

b)

$10110_2$

c)

$147_8$

d)

$A9CF_{16}$

3.

Which of the following number system has base of 2.

a)

$297_{10}$

b)

$10110_2$

c)

$147_8$

d)

$A9CF_{16}$

4.

Which of the following number system has base of 8.

a)

$297_{10}$

b)

$10110_2$

c)

$147_8$

d)

$A9CF_{16}$

5.

Which of the following number system has base of 16.

a)

$297_{10}$

b)

$10110_2$

c)

$147_8$

d)

$A9CF_{16}$

6.

$11101001\ \rightarrow\ Hex$

a)

E9

b)

D8

c)

AC6

d)

F10

7.

$169_{10}\ \rightarrow\ binary$

a)

10101001

b)

10010101

c)

1100101

d)

1011010

8.

$36_{10}\ \rightarrow\ binary$

a)

100100

b)

100010

c)

101000

d)

100001

9.

$777\ \rightarrow\ BCD$

a)

0111 0111 0111

b)

1100 0010 0100

c)

0011 0011 0011

d)

1100 1110 0100

10.

$55\ \rightarrow\ BCD$

a)

0101 0101

b)

1101 0110

c)

0011 0111

d)

1010 0101

11.

$300_{10}\ \rightarrow\ Hex$

a)

12C

b)

11E

c)

10F

d)

1B4

12.

The logic symbol shown is _____.

a)

NOR Gate

b)

OR Gate

c)

NAND Gate

d)

AND Gate

13.

AND gate is represented by switches connected in _____.

a)

series-parallel

b)

parallel

c)

series

d)

all of the choices

14.

AND gate will only operate when ______

a)

both S1 and S2 are closed

b)

both S1 and S2 are open

c)

S1 is closed
S2 is open

d)

S1 is open

S2 is open

15.

OR gate will only operate when ______

a)

either S1 or S2 or both are closed.

b)

both S1 and S2 are open

16.

What switch/s needs to be closed for the lamp to be OFF?

a)

both S1 and S2 are closed

b)

both S1 and S2 are open

17.

The figure represents _____.

a)

NOT Gate

b)

AND Gate

c)

NAND Gate

d)

NOR Gate

18.

Fill in the truth table below for an AND Gate:

a)

1

0

b)

0

1

c)

1

0

d)

0

1

19.

What logic symbol is represented by the figure?

a)

NAND

b)

NOR

c)

AND

d)

OR

20.

OR gate is represented by switches connected in _____.

a)

series

b)

parallel

c)

series-parallel

d)

parallel-series

21.

OR gate will only operate when _____

a)

it is connected to AND gate

b)

both S1 and S2 are open

c)

either S1 or S2 or both are closed

d)

all of the choices

22.

The symbol below is _____.....

a)

AND gate

b)

OR gate

c)

NOT gate

d)

NAND gate

23.

Fill in the truth table for the OR gate:

a)

0

1

b)

1

0

c)

1

0

d)

1

0

1

24.

Fill in the truth table for the NOT gate shown:

a)

1

b)

0

1

c)

1

0

d)

0

25.

Fill in the truth table for the NAND gate shown:

a)

0

1

b)

1

0

c)

1

0

d)

0

1

26.

The logic symbol below shows the ____:

a)

AND Gate

b)

NAND Gate

c)

NOR Gate

d)

OR Gate

27.

What logic symbol is shown below?

a)

AND

b)

OR

c)

NAND

d)

NOR

28.

Fill in the truth table below for NOR Gate:

a)

1

0

b)

0

1

c)

1

0

d)

0

1

29.

Which logic gate is represented by the TT shown?

a)

NOR

b)

OR

c)

AND

d)

NAND

30.

Which logic gate is represented by TT shown?

a)

OR

b)

AND

c)

NOR

d)

EXOR

31.

Which logic gate is represented by TT shown?

a)

OR

b)

AND

c)

NOR

d)

EXOR

32.

Which logic gate is represented by TT shown?

a)

OR

b)

AND

c)

NOT

d)

EXOR

33.

Which logic gate is represented by TT shown?

a)

NOR

b)

NAND

c)

NOT

d)

EXOR

34.

Which logic gate is represented by TT shown?

a)

NOR

b)

NAND

c)

NOT

d)

EXOR

35.

A Schmitt trigger device is one having an output that can be ________

a)

in one of two fixed voltages

b)

both of two fixed voltages

c)

fixed to one voltage

d)

none of the choices

36.

As can be seen from the figure, the output voltage changes ___________ with the change in the input voltage.

a)

incrementally

b)

very slowly

c)

almost instantaneously

d)

all of the choices

37.

The figure below shows the ____.

a)

NOR Gate Characteristics

b)

AND characteristics

c)

NAND Gate Transfer Characteristics

d)

Schmitt NAND Gate Characteristics

38.

Referring to figure:
___________ with the change in the input voltage.

a)

there is a delay in the output voltage

b)

output voltage changes almost instantaneously

c)

the output voltage is cycling

d)

none of the choices.

39.

The input voltage value at which a change in the output state is triggered is referred to as the _______.

a)

input threshold voltage

b)

peak voltage

c)

open circuit voltage

d)

none of the choices

40.

______ is the difference in voltage between the rising threshold voltage and the falling threshold voltage

a)

voltage difference

b)

potential difference

c)

Hysteresis voltage

d)

none of the choices

41.

The benefits of Schmitt trigger device over a standard NAND gate are the following: EXCEPT

a)

Schmitt trigger device is not immune to slowly changing input voltage within the hysteresis voltage

b)

Schmitt trigger device does not eliminate noise

c)

Schmitt trigger device output voltage does not changefaster with the change in the input voltage.

d)

Schmitt trigger device is immune to the not even triggering caused by noise

42.

The Boolean expression below is for ______:
$Output\ =\ S_1\circ\ S_2$

a)

OR gate

b)

AND gate

c)

NAND gate

d)

XOR Gate

43.

The Boolean expression below is for ______:
$Output\ =\ S_1+\ S_2$

a)

OR gate

b)

AND gate

c)

NAND gate

d)

XOR Gate

44.

The Boolean expression below is for ______:
$Output\ =\ \overline{S_1}$

a)

OR gate

b)

AND gate

c)

NAND gate

d)

NOT gate

45.

The Boolean expression below is for ______:
$Output\ =\ \overline{S_1\circ S_2}$

a)

OR gate

b)

AND gate

c)

NAND gate

d)

NOT gate

46.

The Boolean expression below is for ______:
$Output\ =\ \overline{S_1+S_2}$

a)

OR gate

b)

NOR Gate

c)

NAND gate

d)

NOT gate

47.

The logic symbol shown is:

a)

AND Gate

b)

NAND Gate

c)

NOR Gate

d)

OR Gate

48.

Fill in the truth table below for a EXOR Gate

a)

ON

OFF

ON

OFF

b)

OFF

ON

OFF

c)

OFF

ON

d)

ON

OFF

ON

49.

______________are made up from basic logic NAND, NOR or NOT gates that are “combined” or connected together to produce more complicated switching circuits.

a)

Parallel Circuits

b)

Series Circuit

c)

Combinational Circuits

d)

Series Logic Gate Circuits

50.

Identify the logic symbol shown:

a)

EX-NAND

b)

EX-AND

c)

EX-NOR

d)

EX-OR

51.

the EX-OR gate will only operate when _______.

a)

S1 and S2 and S3 are closed

b)

S1 or S2 or both are closed

c)

S1 and S2 are both closed

d)

S1 or S2 are closed but NOT both.

52.

In general, an Ex-OR gate will give an output value of logic “1” ONLY when there are an ________ of 1’s on the inputs to the gate, if the two numbers are equal, the output is “0”.

a)

odd number

b)

even number

c)

equal number

d)

none of the choices

53.

The logic symbol shown is:

a)

EX-NOR

b)

EX-OR

c)

NOR

d)

OR

54.

Fill in the truth table below for EX-NOR gate.

a)

OFF

ON

b)

ON

OFF

ON

c)

OFF

ON

OFF

d)

OFF

ON

OFF

ON

55.

______ will only operate when both S1 AND S2 are closed OR both S1 AND S2 are open.

a)

EX-NOR

b)

EX-OR

c)

OR

d)

NOR

56.

As the _______ gives an output of logic level “1” whenever its two inputs are equal.

a)

NOR

b)

NAND

c)

EX-NOR

d)

EX-OR

57.

_______ gates are used in Digital Comparator circuits.

a)

NOR

b)

NAND

c)

EX-NOR

d)

EX-OR

58.

In a decoder, 4 inputs = ____ outputs

a)

16

b)

2

c)

4

d)

8

59.

In a decoder, 4 inputs = ____ outputs

a)

16

b)

2

c)

4

d)

8

60.

What are the number of input lines for an Encoder circuit if it has three (3) number of output lines?

a)

6

b)

3

c)

8

d)

1

61.

What circuit is indicated by the figure.?

a)

4-2 line decoder

b)

2-1 line decoder

c)

2-1 line encoder

d)

4-2 line encoder

62.

What circuit is indicated by the figure.?

a)

1-2 line decoder

b)

2-1 line decoder

c)

2-1 line encoder

d)

4-2 line encoder

63.

What circuit is indicated by the figure.?

a)

1-2 line decoder

b)

2-4 line decoder

c)

2-1 line encoder

d)

4-2 line encoder

64.

Fill in the truth table for a 2-1 line encoder.

a)

0

b)

0

1

c)

1

0

d)

1

0

65.

At any time, _______ can be ‘1’ in order to get the respective binary code at the output line.

a)

both inputs

b)

2 inputs

c)

only one of its input

d)

none of the inputs

66.

Fill in the truth table below for the 4-2 line decoder.

a)

0 0

0 1

1 0

1 1

b)

0 1

0 0

1 1

1 0

c)

1 1

1 0

0 1

0 0

d)

0 0

1 1

0 1

1 0

67.

Fill in the truth table below for the 1-2 line decoder.

a)

0 1

1 0

b)

0 0

1 1

c)

1 0

d)

1 0

0 1

68.

Fill in the truth table below for the 1-2 line decoder.

a)

0 1 0 1

0 1 0 0

0 0 1 1

1 1 1 0

b)

0 0 0 0

1 1 0 0

0 1 0 1

1 1 1 1

c)

0 0 1 0

1 1 0 0

1 0 1 1

0 0 0 1

d)

0 0 0 1

0 0 1 0

0 1 0 0

1 0 0 0

69.

A Half adder circuit is a __________that can add two “one-bit binary” numbers from its two inputs

a)

logic comparison circuit

b)

binary adding circuit

c)

binary subtractor circuit

d)

multiplexer circuit

70.

A Half Adder circuit is made from an EX-OR gate providing the SUM output of the inputs “A & B” and an _______________.

a)

NOT gate providing the SUM output

b)

NAND gate providing the CARRY output

c)

AND gate providing the CARRY output

d)

OR gate providing the CARRY output

71.

A single-bit full adder circuit can be made by two HALF ADDER circuits and an _______

a)

NAND gate

b)

OR gate

c)

NOR gate

d)

AND gate

72.

A full adder circuit is a binary adding circuit that performs an addition operation on ________ numbers

a)

three one-bit binary

b)

two one-bit binary

c)

one one-bit binary

d)

four one-bit binary

73.

What does the diagram here show?

a)

half-subtractor

b)

full-subtractor

c)

half-adder

d)

full-adder

74.

What circuit is shown:

a)

Full-adder circuit

b)

half-adder circuit

c)

half-subtractor circuit

d)

full-subtractor circuit

75.

fill in the truth table below for the half-adder circuit

a)

1 1

0 1

0 0

1 0

b)

1 0

0 0

0 1

c)

0 0

1 0

0 1

d)

0 0

1 1

0 1

1 0

76.

WHat figure is shown?

a)

full adder

b)

half adder

c)

full subtractor

d)

half subtractor

77.

a ______ can add three “one-bit binary” numbers from its three inputs “A, B & Cin”

a)

full-subtractor

b)

half adder

c)

full-adder

d)

half-subtractor

78.

What is one advantage of full-adder circuit?

a)

It is capable of producing an output of SUM and CARRY-OUT

b)

It eliminates the need for logic gates

c)

It can only add one-bit binary numbers

d)

It requires no input carry

79.

Refer to figure.

the Cout will only be at logical 1, _________

a)

if only one of the inputs is high

b)

if any of the two inputs (A, B & Cin) OR all of the three are HIGH.

c)

if all inputs are low

d)

if one input is high and 2 inputs are low

80.

In JK flipflop, J stands for _____ and K stands for _____.

a)

set, set

b)

clear, set

c)

set, clear

d)

clear, clear

81.

In JK Flipflop, what does CLK stand for?

a)

clock input terminal (clock pulse)

b)

clicking pulse

c)

output terminal

d)

clock battery

82.

what is the figure shown below?

a)

D FLip FLop

b)

SR Flip Flop

c)

JK Flip FLop

d)

none of the choices

83.

J-K flip-flop circuit can be made using _________

a)

2 NAND gates

b)

3 NAND gates

c)

4 NAND gates

d)

3 NOR gates

84.

This is the truth-table for JK Flip Flop.
Determine the outputs 1/2/3/4

a)

1 - No change

2 - reset

3 - Set

4 - Toggle

b)

1 - reset

2 -toggle

3 - no change

4 - set

c)

1 - toggle

2 - reset

3 - no change

4 - Toggle

d)

1 - reset

2 - set

3 - no change

4 - Toggle

85.

this figure shows a JK flip flop converted to a ________.

a)

none of the choices

b)

D type and its truth table

c)

SR type and its truth table

d)

A type and its lies table

86.

The D Type flip flop is a slight modification of the J-K flip flop by inserting an ______ between J and K

a)

inverter

b)

AND gate

c)

NAND gate

d)

NOR gate

87.

what do the following outputs stand for?

a)

1 - reset

2 - set

b)

1 - set

2 - reset

c)

1 - set

2 - set

d)

1 - reset

2 - reset

88.

When groups of these devices are connected together and used to store digital data they are referred to as _____

a)

phrases

b)

sentences

c)

registers

d)

paragraphs

89.

The complete data stored by the group is referred to as a _______

a)

word

b)

letter

c)

register

d)

alphabet

90.

A register enabling shifting of the bits within the register is referred to as a _______.

a)

JK flipflop

b)

shift register

c)

register card

d)

word

91.

Shift registers can be constructed using clocked D-type or ______.

a)

1 OR gate

b)

2 NAND gates

c)

JK Flip Flops

d)

D flip flops

92.

What is "A"?

a)

SIPO

b)

PISO

c)

SISO

d)

PIPO

93.

after the 5th clock pulse is generated, ______.

a)

the input to D-type A is at logic 1

b)

it will have been shifted completely out of the register.

c)

the input to D-type A is at logic 1 and this will be transferred to its output QA.

d)

the input to D-type A is at logic 0

94.

the count output after the 6th clock pulse is ______

a)

0000

b)

1000

c)

0110

d)

1010

95.

the count output after the 7th clock pulse is ______

a)

0000

b)

1000

c)

0111

d)

1010

96.

the count output after the 8th clock pulse is ______

a)

0000

b)

1000

c)

1110

d)

1010

97.

The total output from the shift register shown is:

a)

15

b)

8

c)

4

d)

2

98.

110111 to decimal = ____....

a)

157

b)

63

c)

115

d)

119

99.

sequential circuit that loads the data present on its inputs and then moves or “shifts” it to its output once every clock cycle

a)

closed circuit

b)

shift register

c)

encoder

d)

decoder

100.

_____________ Shift Register circuit, is a circuit that moves/shift the data serially “IN” and “OUT” one bit at a time under clock control

a)

SIPO

b)

SISO

c)

PISO

d)

PIPO

101.

Hex A3 to decimal?

a)

153

b)

161

c)

163

d)

173

102.

255 decimal to HEX

a)

FF

b)

FE

c)

EF

d)

F1

103.

Decimal 93 to BCD

a)

1001 0011

b)

1001 1001

c)

1001 0101

d)

1001 1000

104.

decimal 150 --> binary

a)

10010110

b)

10010100

c)

10011010

d)

10011110

105.

10111100 to decimal

a)

188

b)

184

c)

192

d)

186

106.

octal 75 to decimal

a)

61

b)

65

c)

77

d)

53

107.

72 to binary

a)

1001000

b)

111000

c)

100110

d)

110010

Circuitos Lógicos

Total questions: 107

Worksheet time: 54mins

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