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WorksheetsCE201_SU24_FE
Total questions: 50
Worksheet time: 4hrs 10mins
Which of the following components was used in the first ENIAC computer?
Bipolar transistors
Field transistors
Vacumn tubes
Semiconductor lcs
Which of the following statements is true for Von Neuman architecture?
Shared bus between the program memory and data memory
Separate bus between the program memory and data memory
External bus for program memory and data memory
External bus for data memory only
Which of the following components does not belong to central?
System interconnection
ALU
Registers
Control Unit
CPU interconnection
Central Processing Unit (CPU) of IAS computer consists of ...
Main memory and ALU
ALU and Control Unit (CU)
CU and IO Module
ALU and IO Module
The first generation of computers used ... for digital logic elements and memory
Transistors
Interated circuits
Large-scale integration
Vacumn Tubes
In the computer, what categories do external devices include? (Choose 3 correct answers)
Human readable
Communication
Data Conversion
Machine readable
Which of the folllowing determines the Bus Width?
The clock speed of the CPU
The number of cores in the processor
The size of the motherboard
The number of parallel lines in the data bus
Number of components connected to bus
In the CPU, what is the functionality of the control unit?
To decode program instructions
To control the sequence of operations
To store program instruction
To transfer data to primary storage
The basic components of a computer are:
Main memory, CPU, I/O modules and system interconnection
Main memory, CPU, I/O modules and Storage device
Main memory, CPU, Peripherals and Storage device
Main memory, CPU, I/O modules and Storage device
What is the correct order of memory access speed from fastest to lowest?
Registers > Cache > RAM > SSD
Cache > Registers > RAM > SSD
Registers > Cache > SSD > RAM
Cache > Registers > SSD > RAM
All of the mentioned are wrong
What is the cache memory level that is integrated into the processor chip and has the lowest latency?
L1 cache
L2 cache
L3 cache
L4 cache
Which of the following components of CPU is responsible to direct the system to execute instructions?
ALU
Control Unit
Registers
RAM
Consider a machine with a byte addressable main memory of 2^16 bytes and block size of 8 bytes. Assume that a direct mapped cache consisting of 32 lines is used with this machine. How many bits are there in the line field of the cache?
3
4
5
6
7
For reads to and writes from main memory, ... translates each virtual address into a physical address in main memory.
MAR
MMU
Overlays
TLB
Accumulator
What is the main idea of using Hamming code for error correction?
Adding extra parity bits to the data bits such that the number of 1s in each subset of bits is even
Adding extra parity bits to the data bits such that the number of 1s in each subset of bits is odd
Adding extra parity bits to the data bits such that the parity bits form a binary number indicating the position of the error bit
Adding extra parity bits to the data bits such that the parity bits form a binary number indicating the number of error bits
What are the key differences in the architecture of NOR and NAND flash memory?
NOR flash memory cells are connected in series, while NAND flash memory cells are connected in parallel
NOR flash memory cells are connected in parallel, NAND flash memory cells are connected in series
Both NOR and NAND flash memory cells are connected in series
Both NOR and NAND flash memory cells are connected in parallel
All of the mentioned are wrong
Which memory has the fastest speed and smallest capacity?
Cache
Main memory
HDD
Magnetic Disk
... is a set of physical disk drives viewed by the operation system as a single logical drive.
CLV
SSD
RAID
CAV
Sort the following memory types in ascending order by access speed:
HDD - Main Memory - L2 cache - L1 cache
HDD - Main Memory - L1 cache - L2 cache
HDD - L2 cache - L1 cache - Main Memory
MainMemory - L2 cache - L1 cache - HDD
Which is the correct choice for sorting in increasing speed average of memory?
SSD < Main Memory < Cache < Magnetic Tape
Magnetic Tape < SSD < Cache Memory < Main Memory
Magnetic Disk < SSD < Cache Memory < Main memory
Magnetic Disk < Magnetic Tape < Main Memory < Cache Memory
Magnetic Disk < SSD < Main Memory < Cache Memory
For the following Boolean expressions: AB + AB' and the truth table:
Choose the correct option to replace at "?"
1, 1 , 0, 0
1, 1, 1, 1
1, 0, 1, 0
0, 1, 1, 0
If you have a boolean function with 3 variables, how many rows are there in the truth table?
8
3
6
12
In isolated I/O, ...
The I/O devices and the memory share the same address space
The I/O devices have a separate address space from memory
The memory and I/O devices have an associated address space
A part of the memory is specifically set aside for the I/O operation
None of the mentioned
Which component defines the system call interface to the operating system and facilitates binary portability?
Application Binary Interface
Application Programming Interface
Instruction Set Architecture
Central Processing Unit
What is the initial state of a process when it is admitted by the high-level scheduler, but not yet ready to execute?
New
Ready
Running
Halted
The chunks of a program, known as pages, could be assigned to available chunks of memory, known as frames, is called ...
Swapping
Partitioning
Paging
Virtual Memory
Segmentation
How does Boolean algebra contribute to the design of digital circuits?
It simplifies the implenmentation of desired functions
It helps in the analysis of economic data
It facilitates the design of analog circuits
It is primarily used for chemical engineering and physical engineering
When both inputs are 1, what is the result of a NAND gate?
0
1
2
Undefined
#NA
Express a sign integer number (+18) in the sign magnitude representation.
00010010
10010010
11110010
01110010
Why is it essential to use symbolic representation of machine instructions?
It makes machine instructions more human-readable and understandable
It reduces the overall complexity of computer systems and user programs
It minimizes the need for memory storage for the user programs
It enables fastest execution of high level language instructions
The hardware mechanism that allows a device to notify the CPU is called ...
polling
interrupt
driver
controlling
What is a branch instruction?
The instruction that are used to divide a program into multiple subprograms
The instruction that have as one of its operands the address of the next instruction to be executed
The instruction that are used to pause the program
The instruction that are used to return to the beginning of the program
The effective address of ... is:
EA = A + (R)
(R) <-- R + 1
relative addressing
autoindexing
postindexing
preindexing
In MASM32, which OPCODE is used to compare 2 values?
COM
CMP
IF ... ELSE
TEST
What is the role of the control unit in a processor?
The control unit's primary role is to perform arithmetic and logical operations within the processor, orchestrating the manipulation of the data
The control unit only manages the flow of data between the CPU and external devices and does not play a significant role in executing instructions
The control unit is solely responsible for managng the flow of instructions from secondary storage to RAM and does not have a role in the internal operation of the CPU
The control unit in a processor directs and coordinates the execution of instructions, interpreting and managing the flow of operations within the CPU
How data registers and address registers differ in some computer systems?
Address registers can be employed in calculating operand addresses, while data registers hold data
Data registers are only used for stack-related operations
Data registers are used for indexed addressing, while address registers are used for data storage
Address registers are reserved for segmented addressing, while data registers are general-purpose
What is the main benefit of using ARM processors over other processors?
Low cost and low power consumption
Higher degree of multi-tasking
Lower error or glitches
Efficient memory management
Which statement is incorrect about RISC and CISC architecture?
CISC architecture is more convenient for programmers than RISC architecture
CISC architecture has more operands in a instruction compared to RISC architecture
CISC architecture has a more flexoble instruction set than RISC architecture
CISC architecture requires more general-purpose registers than RISC architecture
In the concept of Register Window, how many register groups are there?
4
3
2
No distinction
What is the main benefit of using RISC over CISC?
RISC has more instructions and addressing modes than CISC
RISC has faster instruction execution and simplier instruction decoding than CISC
RISC has variable-length instruction formats abd direct memory access than CISC
RISC has more registers and pipelines than CISC
What is the benefit of using a superscalar organization over a scalar organization?
It increases the instruction throughput and improves the performance
It reduces the power consumption and the heat dissipation
It simplifies the instruction set and compiler design
All of the mentioned
None of the mentioned
What does the term "instruction-level parallelism" refer to in computer architecture?
The degree to which instructions in a program can be executed in parallel
The number of processor cores in a multi-core CPU with multiple resources
The complexity of the instruction set architecture
The lenght of an instruction cycle with high level programming language
To enhance performance in a superscalar processor, which method(s) should we apply?
Duplication of resources
Out-of-order issue
renaming registers
All of the mentioned
How many common classifications of parallel systems are there as proposed by Flynn?
2
3
4
5
Which write technique in which all write operations are made to main memory as well as to the cache, ensuring that main memory is always valid?
Write through
Write back
Write around
No write allocate
How does multithreading improve the performance of a processor?
It increases the instruction-level parallelism by issuing multiple instructions fron different threads in the same cycle
It increases the thread-level parallelism by executing multiple threads on different cores or processors
It increases the utilization of the processor resources bt hiding the latency of long-latency events such as cache misses or branch mispredictions
All of mentioned
Follow the Amdahl's law for multiprocessors, if only 10% of the code is inherently serial (f=0.9), running the program on a multicore system with 4 processors, a performance gain (speedup factor) would be ...
307%
297%
317%
327%
Which cache is not a shared cache?
L4 cache
L3 cache
L2 cache
L1 cache
CPU of IAS computer consists of ...
Main memory and ALU
ALU and CU
CU and IO Module
ALU and IO Module
What is the significance of the program counter (PC) in the fetch phase of the instruction cycle?
PC is not used in the fetch phase, and its role is limited to tracking the number of instructions executed bt the CPU
PC in the fetch phase holds the memory address of the next instruction to be fetched and executed
PC is responsible for executing instructions and has no specific role during the fetch phase
PC is only relevant in multi-core processors and does not contribute to the fetch phase of the instruction cycle in single-core systems
