WorksheetsFT1-21ECC303T
Total questions: 40
Worksheet time: 13mins
Name
Class
Date
1.
What will be printed by the following code?
module test;
reg [3:0] a = 4'b1101;
initial $display("%b", a >> 1);
endmodule
a)
1101
b)
110
c)
1011
d)
11
2.
In Verilog, what is the output of this code?
assign y = ~(4'b1010 & 4'b1100);
a)
4'b0101
b)
4'b0011
c)
4'b1111
d)
4'b0110
3.
Consider:
always @(*) begin
a = 1; b = a + 2;
end
— What is the value of `b` after execution?
a)
1
b)
2
c)
3
d)
4
4.
Which of the following code correctly describes a 2-to-1 MUX in behavioral modeling?
a)
assign y = s ? d1 : d0;
b)
always @(s or d1 or d0) y = s ? d1 : d0;
c)
always @(posedge clk) y <= d1;
d)
y = s ? d1 : d0;
5.
What is the output of:
`assign y = ^4'b1101;
a)
1
b)
0
c)
x
d)
z
6.
In the code:
reg [3:0] a = 4'b1001;
initial a = a << 1;
what is `a` after execution?
a)
1001
b)
10
c)
1010
d)
100
7.
For `assign y = {2{2'b10}};
, what is `y`?
a)
1010
b)
101010
c)
10101010
d)
10
8.
What does the following code implement?
`assign y = ~(a ^ b);`
a)
XOR
b)
XNOR
c)
AND
d)
OR
9.
What is the output for:
`assign y = (3'b101 == 3'b101);`
a)
0
b)
1
c)
x
d)
z
10.
Given: always @(posedge clk) q <= d;
— What is implemented?
a)
Combinational logic
b)
D Flip-Flop
c)
Latch
d)
Counter
11.
What is printed by:
integer i;
initial for(i=0;i<3;i=i+1) $display(i);
a)
0 1 2
b)
1 2 3
c)
0 1 2 3
d)
2 1 0
12.
Which modeling type is used in: and a1(out, in1, in2);
a)
Behavioral
b)
Dataflow
c)
Gate-level
d)
Switch-level
13.
For:
assign y = &4'b1011;
what is `y`?
a)
0
b)
1
c)
x
d)
z
14.
What does `{a,b}` represent in Verilog?
a)
Concatenation
b)
Replication
c)
Reduction
d)
None
15.
What will be the initial value of `reg [3:0] r;` if not assigned?
a)
0
b)
1
c)
x
d)
z
16.
In `assign y = #5 a & b;`, when is `y` updated?
a)
Immediately
b)
After 5 time units
c)
Before 5 time units
d)
Never
17.
Given: `assign y = a ? b : c;` — This implements:
a)
AND gate
b)
2-to-1 MUX
c)
OR gate
d)
Latch
18.
In Verilog, `reg clk = 0; always #5 clk = ~clk;` — period of clk is:
a)
5
b)
10
c)
15
d)
20
19.
What is the value of `y` in `assign y = a ^ a;`?
a)
1
b)
0
c)
x
d)
z
20.
The statement `x <= x + 1;` in a clocked always block means:
a)
Blocking assignment
b)
Non-blocking assignment
c)
Infinite loop
d)
Comparison
21.
For:
initial begin a = 1;
#10 a = 0;
end
— when does `a` become 0?
a)
Time 0
b)
Time 1
c)
Time 5
d)
Time 10
22.
What is the result of `assign z = 4'b0110 ^ 4'b1001;`
a)
4'b1111
b)
4'b0111
c)
4'b1100
d)
4'b0000
23.
In: `always @(posedge clk) q = d;` — which type of assignment is used?
a)
Blocking
b)
Non-blocking
c)
Continuous
d)
None
24.
In Verilog, `casez` allows:
a)
Don’t care bits
b)
Only 1 or 0
c)
Only x
d)
Only z
25.
The operator `{3{2'b01}}` produces:
a)
10101
b)
101010
c)
111111
26.
Which keyword is used to end a module?
a)
end
b)
endcase
c)
endmodule
d)
finish
27.
For: `assign y = a && b;` — operator type is:
a)
Logical AND
b)
Bitwise AND
c)
Reduction AND
d)
None
28.
In: `always @(posedge clk) q <= ~q;` — function is:
a)
D Flip-Flop
b)
T Flip-Flop
c)
Counter
d)
Latch
29.
The default value of wire is:
a)
0
b)
1
c)
x
d)
z
30.
Which operator is `~^` in Verilog?
a)
NOR
b)
XNOR
c)
XOR
d)
NAND
31.
What is the output of: `assign y = (4'd5 > 4'd3);`
a)
0
b)
1
c)
x
d)
z
32.
Which gate does `assign y = ~(a & b);` represent?
a)
NOR
b)
NAND
c)
AND
d)
OR
33.
In: `#10 a = 1;` — delay is:
a)
1 time unit
b)
10 time units
c)
0 time units
d)
Undefined
34.
For: `always @(posedge clk or negedge rst) if (!rst) q <= 0; else q <= q+1;` — This is:
a)
Asynchronous reset counter
b)
Synchronous reset counter
c)
Latch
d)
Decoder
35.
`assign y = a | b;` represents:
a)
OR
b)
AND
c)
XOR
d)
XNOR
36.
`assign y = a & b | c;` — precedence gives:
a)
(a & b)
b)
(b | c)
c)
(a & b) | c
d)
c
37.
The construct `always @(*)` is used for:
a)
Sequential logic
b)
Combinational logic
c)
Latches
d)
None
38.
`assign y = a + b;` — type of modeling:
a)
Gate-level
b)
Dataflow
c)
Behavioral
d)
Switch-level
39.
Which statement is true for `initial begin ... end`?
a)
Executes once at simulation start
b)
Executes continuously
c)
Executes at every clock edge
d)
None
40.
Which operator is used for bitwise AND?
a)
&
b)
&&
c)
|
d)
||
100 %
