WorksheetsVerilog Logic and Circuit Quiz
Total questions: 15
Worksheet time: 8mins
Which Verilog construct is best suited to model combinational logic like adders or multiplexers?
always @(posedge clk)
initial block
assign statement
always @(posedge reset)
In a 4-bit adder/subtractor circuit, the control input is XORed with each bit of operand B. What is the purpose of this operation?
To detect carry propagation
To enable signed number operations
To convert addition into subtraction
To avoid overflow
In a full subtractor, the borrow output depends on:
Only A and B
Only Bin and A
A, B, and Bin
A and Bin only
Which flip-flop is most efficient to implement counters in Verilog?
SR flip-flop
D flip-flop
JK flip-flop
T flip-flop
If a T flip-flop receives continuous clock pulses with T = 1, the output will:
Remain constant
Reset to 0 always
Toggle between 0 and 1
Produce unpredictable results
A 2:1 multiplexer can be used to implement:
XOR gate
NOT gate
Any Boolean function
NAND gate
In the 4×1 multiplexer, if S1S0 = 10, which input is selected?
I0
I1
I2
I3
A shift register is mainly used for:
Error detection
Data storage and transfer
Frequency division
Performing subtraction
Which counter produces a sequence like 1000 → 0100 → 0010 → 0001?
Ripple counter
Ring counter
Johnson counter
Synchronous counter
The main difference between ring counter and Johnson counter is:
Johnson counter uses feedback of complemented output
Ring counter is synchronous, Johnson is asynchronous
Johnson counter cannot be implemented in Verilog
Ring counter always counts downward
In Verilog, which sensitivity list ensures combinational behavior?
always @(posedge clk)
always @(*)
always @(posedge reset)
always @(negedge clk)
A 3-bit asynchronous counter implemented with T flip-flops will have how many distinct states?
4
6
7
8
The output of a JK flip-flop when J = K = 1 is:
Reset
Set
No change
Toggle
Which of the following circuits can be built using only multiplexers?
Half adder
Full adder
Decoder
All of the above
If a D flip-flop receives input D = 1 and clock pulses continuously, the output Q will:
Remain at 1 after first clock
Oscillate between 0 and 1
Depend on reset only
Be unpredictable
