In Register Indirect Addressing, the operand is:

Which addressing mode requires two memory accesses — one to fetch the address and one to fetch the operand?

The instruction ADD R1, (R2) uses which addressing mode?

If memory location 200 holds address 500, and memory[500] = 25, what will LOAD R1, (200) load into R1?

In Direct Addressing, if instruction says LOAD R2, 300 and M[300]=45, R2= ?

The instruction MOV A, #5 is an example of:

In Implicit Addressing, the operand:

During which phase of the instruction cycle is the instruction decoded?

The Program Counter (PC) is incremented during the:

The Instruction Register (IR) temporarily holds:

The Execute phase may involve:

If instruction fetch requires 1 μs, decode 0.5 μs, execute 1.5 μs, and store 0.5 μs — total instruction cycle time = ?

If PC = 1200 before fetch, what is PC after fetching one instruction?

A zero-address instruction is most suitable for which architecture?

In a one-address instruction, one operand is assumed to be in:

The instruction MUL R1, R2 can belong to which format?

Three-address instructions are generally:

How many addresses are needed for the instruction R3 = R1 + R2?

If an instruction has opcode 8 bits and 3 address fields of 12 bits each, total instruction size = ?

A single accumulator organization uses:

RISC architecture typically uses:

CISC stands for:

Which of the following is not a feature of RISC?

If a RISC instruction takes 1 cycle and a CISC instruction takes 4 cycles but replaces 3 RISC instructions, which is faster for total of 12 operations?

In Von Neumann architecture, instructions and data share:

The Harvard architecture uses:

A major disadvantage of Von Neumann architecture is:

The Harvard architecture is commonly used in:

If instruction and data buses are separate, how many memory fetches occur simultaneously?

A shift register is primarily built using:

The main function of a shift register is:

A SISO shift register outputs data:

In SIPO, data is input:

If 4-bit SISO register input = 1010, what is serial output sequence?

A 4-bit SIPO receives input 1001. After 3 pulses, what is output?

In a PISO register, parallel input = 1011. What will be the serial output after one clock?

In a PIPO shift register, data is:

Counters are made of which flip-flop?

In a 4-bit counter, how many states are possible?

A 3-bit synchronous counter counts from:

Minimum number of flip-flops for mod-10 counter = ?

A mod-6 counter counts up to decimal:

If 4-bit asynchronous counter output = 1111, next output (up count) = ?

In a synchronous counter, all flip-flops are:

Ripple counter is also called:

Booth’s algorithm is used for:

Booth’s algorithm improves:

Multiply 3 × 2 (0011 × 0010) = ?

Multiply (-3) × (2) in 4-bit 2's complement → product = ?

The non-restoring division method avoids:

Divide 8 ÷ 3 using non-restoring division → quotient = ?

In restoring division, when partial remainder < 0, we:

Booth algorithm is particularly efficient for:

The IAS instruction length is:

If AC = 10, M(X) = 7, result of ADD M(X) → ?

The instruction STOR M(X) means:

If AC = 12, M(X) = -5 → result of ADD |M(X)| = ?

The instruction LSH in IAS computer:

If AC = 00001010, after LSH → AC = ?