WorksheetsRe-Assessment
Total questions: 100
Worksheet time: 50mins
What does an assertion do during simulation?
Synthesizes logic
Checks expected behavior
Generates waveform
Optimizes code
Which of the following is a type of assertion in SystemVerilog?
immediate
static
dynamic
soft
Which construct is used to define temporal behavior in assertions?
assert property (a && b);
assert property (a |-> b);
assert (a == b);
assert sequence (a ##1 b);
What does ## represent in a sequence?
Delay operator
Bitwise AND
Logical AND
Concatenation
What does |-> denote in a property definition?
Conjunction
Implication
Delay
Equality
Which assertion type is evaluated in procedural code blocks?
Temporal
Concurrent
Immediate
Static
Which operator allows repetition in a sequence?
[*]
|->
##
==
Which keyword is used to define a reusable assertion block?
property
function
sequence
module
Which system task immediately terminates the simulation upon invocation?
$info
$warning
$fatal
$error
What is the primary purpose of $warning?
To stop simulation
To log non-critical issues
To display debug info
To raise fatal errors
Which task is best used for general informational messages during simulation?
$error
$info
$warning
$fatal
Which of the following does not affect simulation control flow?
$fatal
$warning
$info
$error
What happens when $error is triggered during simulation?
Message is printed and simulation continues
Simulation halts immediately
A warning is issued
All assertions are disabled
Which task is least severe in terms of simulation impact?
$warning
$error
$info
$fatal
What is the primary purpose of functional coverage in SystemVerilog?
To generate waveform data
To measure simulation performance
To track which scenarios have been exercised
To verify timing constraints
Which construct is used to define functional coverage?
coverpoint
cover
covergroup
assert
What does coverpoint represent?
A sequence of events
A sampled variable or expression
A testbench module
A simulation time marker
What is the purpose of bins in a coverpoint?
To group simulation cycles
To store waveform data
To define assertion conditions
To define value ranges or sets to track
Which type of bin is automatically created by the simulator?
explicit
illegal
default
ignore
Which bin type is used to mark invalid or undesired values?
default
cross
ignore
illegal
Which of the following can be used inside a covergroup definition?
coverpoint
cover
initial
always
Which of the following is true about coverage reports?
They show which bins were hit
They are part of synthesis output
They are generated only for assertions
They display all the input combinations
Which keyword is used to define transition bins?
bins with |->
transitions
trans bin
bins with =>
Which of the following is NOT a valid bin type?
default
illegal
ignore
valid
Which of the following can cause cross coverage bins to remain unhit?
Disabled covergroup
All of the above
Missing combinations in stimulus
Incorrect sampling
What is the primary use of a mailbox in SystemVerilog?
Signal routing
Clock generation
Memory allocation
Inter-process communication
What does the get() method do in a mailbox?
Sends a message
Retrieves and removes a message
Deletes the mailbox
Checks mailbox size
Which method checks if a mailbox has messages without removing them?
scan()
peek()
get()
try_get()
What is the primary use of a semaphore in SystemVerilog?
Data storage
Message passing
Clock control
Synchronization
What happens if a process calls get(n) and fewer than n keys are available?
it creates the sufficient number of keys
It blocks until keys are available
It returns immediately
it throws an error
Which method allows non-blocking retrieval from a mailbox?
sample()
try_get()
peek()
get()
Which of the following is true about peek() in mailboxes?
It blocks if mailbox is empty
It removes the message
It reads without removing
It deletes the mailbox
What happens if you try to put an incompatible type into a parameterized mailbox?
Compilation error
It is silently ignored
It is automatically cast
Runtime warning
Which of the following statements about covergroup is true?
It can only track one variable
It cannot be used with assertions
It is mandatory for all simulations
It is used for functional coverage
What does the sample() method do in the context of a covergroup?
It triggers the covergroup to record data
It displays the coverage report
It retrieves the last sampled value
It resets the covergroup
What is the result of calling put() on a full mailbox?
It throws an error
It returns null
It overwrites the oldest message
It blocks until space is available
Which of the following is a valid way to define a covergroup in SystemVerilog?
cover my_group { coverpoint a; }
covergroup my_group; coverpoint a; endgroup;
group my_group { coverpoint a; }
covergroup my_group { coverpoint a; }
Two threads call sem.get(1) simultaneously. What happens?
One thread blocks
Simulation fails
Semaphore resets
Both threads proceed
You define a cross coverage: "cross mode, enable;" After simulation, some cross bins are unhit. What’s the best explanation?
mode is constant
enable is never high
Cross coverage is disabled
Certain combinations never occur
You define a covergroup but forget to call sample(). What happens?
All bins are ignored
Coverage is collected automatically
Coverage report shows zero hits
Simulation fails
You define a covergroup to track values of a 2-bit signal: "covergroup cg @(posedge clk); coverpoint mode; endgroup" After simulation, bin[2] is never hit. What’s the best debugging step?
Check if mode is randomized
Replace coverpoint with assert
Use disable iff
Add assert(mode!=2)
Which loop guarantees at least one execution of the loop body?
do...while
while
for
repeat
Which SystemVerilog loop is typically used when the number of iterations is known beforehand?
do...while
while
forever
for
What does the forever statement do?
Continuously repeats the body indefinitely until simulation stops or a break
Repeats body until a timeout
Executes body zero or more times depending on condition
Executes body exactly once
Which control-flow statement in SystemVerilog selects a branch based on a single expression's value?
repeat
if-else
case
fork-join
Which statement best describes unique if?
Forces synthesis-friendly behavior only
A synonym for if
Like if, but requires exactly one branch to evaluate true — else simulation error if none or multiple true.
Prevents else-if chaining
What is the difference between unique and unique0 on an if?
unique0 reports an error if exactly one condition true.
unique reports an error if zero or multiple conditions true; unique0 allows zero true but errors on multiple true.
They are identical.
unique allows multiple true branches; unique0 does not.
What is a priority if used for?
Ensures mutually exclusive priority encoding — later conditions checked only if earlier ones false; suppresses uniqueness checking.
Optimizes performance in simulation only
Forces parallel evaluation of conditions
Declares a sequence of concurrent statements
Which keyword helps the simulator check that if/else if branches are mutually exclusive and flags an assertion if they are not?
unique
parallel
exclusive
priority
In a SystemVerilog task, which of these is allowed?
Returning a value like a function
Containing timing controls such as #, @(posedge ...)
Being used in constant expressions
Being called inside an expression context
Which of the following is TRUE about SystemVerilog function?
A function can contain timing controls like # and @.
A function must return a value (or be declared void) and cannot use timing controls.
A function can return multiple values.
A function call spawns a new thread.
Which statement is true: tasks vs functions?
Both must return a value.
Functions may contain delays; tasks cannot.
Both can contain @ event controls.
Tasks may consume simulation time (delays); functions cannot.
What does an automatic task or function do?
Allocates local variables statically once for entire simulation.
Runs in a separate process automatically.
Prevents the use of fork inside the task.
Allocates local variables per invocation (reentrant).
Which SystemVerilog method of argument passing allows you to specify arguments by their parameter names in any order?
By position
By value only
By reference
By name (.arg(expr))
If a task has prototype task t(int a, int b); which call uses positional argument passing?
t(b:2, a:1);
t(.b(2), .a(1));
t(1, 2);
t(.a(1), .b(2));
Which of the following is a correct description of inout port?
It is the same as input
It creates a new local variable unrelated to the caller
It only passes values out of the task
It allows both input and output usage; the task may read and write the argument
In SystemVerilog, pass-by-position and pass-by-name differ how?
They are identical.
Position matches parameters by order; name matches parameters by explicit parameter names.
Position passes by reference; name passes by value.
Position uses .name() syntax; name uses order-only.
Which statement about fork...join in SystemVerilog is TRUE?
fork...join_none waits for the first child to finish.
fork...join is equivalent to sequential execution.
fork...join spawns parallel threads and join waits for all to complete.
fork...join_any waits for none of the children to finish.
What does fork ... join_any do?
Kills all other threads when one finishes.
Waits for all spawned threads to finish.
Waits for the first spawned thread to finish, then continues; other threads continue running.
Does not wait for any thread; returns immediately.
Which SystemVerilog construct groups signal declarations and procedural code to bundle ports — used for connecting modules?
Interface
Task
Package
Class
What is a modport inside an interface used for?
To instantiate multiple copies of an interface.
A method to declare clocking blocks only.
Declaring different views (directions & signals) of the interface for modules or classes.
Synthesis only directive.
What is a virtual interface in SystemVerilog?
An interface that is synthesized differently.
A purely simulation-only net type that cannot be used in UVM.
A handle (class-like pointer) that allows classes to reference an interface instance at runtime.
A special interface for virtual clocking only.
Which of these best describes a SystemVerilog class instance?
A value type stored in registers like logic
A handle (reference) to an object allocated in dynamic memory via new
Always synthesized into hardware
Only useful for testbench; cannot contain methods
What does static mean when applied to a class variable?
Each object gets its own copy.
The variable is shared across all class instances (class-level).
The variable is read-only.
The variable is virtual.
Which keyword is used in a class to indicate a method is virtual (can be overridden)?
virtual
override
dynamic
polymorphic
What is the scope resolution operator in SystemVerilog?
::
->
.
:
Which of these is a correct use of typedef?
typedef is not supported in SystemVerilog.
typedef class { } MyClass;
typedef int myint; — creates an alias myint for int.
typedef myint int;
In SystemVerilog randomization, what does the rand qualifier do?
Makes a variable read-only.
Marks a variable to be considered by randomize() for value assignment.
Forces a deterministic value.
Indicates the variable is constant.
Which randomize usage allows local constraints for that invocation only?
randomize() with { ... } — the with clause supplies temporary constraints for that call.
rand_mode()
randomize() only
randomize_local()
Which of these fork variants causes the parent process to wait until every child process completes before continuing?
fork ... join_first
fork ... join
fork ... join_any
fork ... join_none
Which keyword marks a class method as not tied to an instance (i.e., callable on the class itself)?
static
local
automatic
virtual
What does the super keyword allow you to do in a derived class?
Refer to the package-level class.
Convert object to parent type.
Access methods and fields of the parent class (call parent constructor or parent method).
Access private members only.
What is an external method in class context?
A method declared in the class with extern and defined outside.
Not supported in SystemVerilog.
A method declared with import.
A method that cannot access class members.
Which SystemVerilog construct allows multiple processes to run concurrently inside a module or initial block?
always only
fork ... join
begin ... end
function only
Which is a correct description of unique0 case?
Errors if zero matches.
Checks uniqueness and allows zero matches but errors on multiple matches.
Not supported.
Same as unique.
Which keyword makes class members only visible to derived classes and the class itself?
local
protected
export
public
How do you declare a typedef for an array type?
typedef int my_arr_t[8];
int typedef my_arr_t[8];
typedef int my_arr_t{8};
Not allowed in SystemVerilog
Where would you use virtual interfaces mainly?
To declare interface templates.
To avoid using import.
For synthesis only.
To permit runtime binding of an interface instance to a class-based testbench component (e.g., driver/monitor).
For constrained random fields, how do you temporarily add a constraint for a single randomize() call?
obj.randomize_inside(x > 10);
Not possible to add temporary constraints.
obj.randomize() with { x > 10; }
obj.randomize_local({x>10});
How are pure virtual methods declared for tasks?
Tasks cannot be virtual.
pure virtual task mytask(); — analogous to functions, tasks can be declared pure virtual to force derived classes to implement them.
task mytask() pure;
Use virtual pure only for functions.
Which statement about the logic data type is correct?
Logic can only be used in continuous assignments
Logic is deprecated in SystemVerilog
Logic can only be used in procedural assignments
Logic can be used in both continuous and procedural assignments
What is the primary advantage of using logic over wire and reg?
Logic uses less memory
Logic supports more bit widths
Logic unifies wire and reg functionality
Logic is faster in simulation
What is the size of a shortint data type in SystemVerilog?
8 bits
32 bits
64 bits
16 bits
What is the precision of shortreal data type?
128-bit quad precision
32-bit single precision
16-bit half precision
64-bit double precision
How are strings stored internally in SystemVerilog?
As unpacked arrays of characters
As dynamic arrays of bytes
As packed arrays of bits
As fixed-size character arrays
What happens when you assign a shorter string to a longer string variable?
The string is truncated
Compilation error occurs
The string is padded with null characters
The string variable resizes automatically
Which of the following is a valid use of void?
void my_var;
function void display_msg();
parameter void PARAM = 5;
void array[10];
What is the default value of the first enumerated constant if not explicitly specified?
1
X
Z
0
Which syntax correctly defines an enumerated type with typedef?
typedef enum {RED, GREEN, BLUE} color_t;
enum color_t {RED, GREEN, BLUE} typedef;
enum typedef {RED, GREEN, BLUE} color_t;
typedef {RED, GREEN, BLUE} enum color_t;
Which array type uses a hash table for storage?
Dynamic array
Associative array
Fixed array
Queue
What symbol is used to declare a queue in SystemVerilog?
[#]
[]
[*]
[$]
Which method adds an element to the front of a queue?
insert()
push_front()
add()
push_back()
When should non-blocking assignments be used?
In sequential logic
In function definitions
In continuous assignments
In combinational logic
What is the difference between packed and unpacked structures?
Packed structures use more memory
Packed structures are slower
There is no difference
Packed structures are stored as contiguous bits
What is the key characteristic of a union in SystemVerilog?
Members must be of the same data type
All members have separate memory locations
All members share the same memory location
Members are accessed sequentially
What is the purpose of the 'initial' block in SystemVerilog?
To create a testbench
To initialize variables at simulation start
To define a module
To define a clock signal
Which array method returns a new array with elements sorted in ascending order?
sort()
shuffle()
reverse()
rsort()
Which method is used to randomize the order of array elements?
reverse()
sort()
rsort()
shuffle()
Which ordering method modifies the array elements in place rather than returning a new array?
rsort()
All of the above
sort()
reverse()
If an enum is declared as: typedef enum {A=1, B=4, C=7} enum_t; What will enum_t.first() and enum_t.last() return?
1 and 7
B and C
A and C
Undefined
