WorksheetsSystemVerilog Assessment 4 – Worksheet Questions
Total questions: 100
Worksheet time: 50mins
Which construct is used to define temporal behavior in assertions?
task
always
initial
sequence
What does ## represent in a sequence?
Delay operator
Bitwise AND
Logical AND
Concatenation
Which of the following is used to monitor coverage of sequences?
coverpoint
covergroup
cover
assert
What does |-> denote in a property definition?
Conjunction
Implication
Delay
Equality
Which assertion type is evaluated in procedural code blocks?
Temporal
Concurrent
Immediate
Static
Which system task immediately terminates the simulation upon invocation?
$info
$warning
$fatal
$error
What is the primary purpose of $warning?
To stop simulation
To log non-critical issues
To display debug info
To raise fatal errors
Which task is best used for general informational messages during simulation?
$error
$info
$warning
$fatal
Which task allows you to specify an exit code when terminating simulation?
$error
$fatal
$warning
$info
Which of the following does not affect simulation control flow?
$fatal
$warning
$info
$error
Which task is most appropriate for logging assertion failures without stopping simulation?
$warning
$info
$error
$fatal
Which task is least severe in terms of simulation impact?
$warning
$error
$info
$fatal
Which construct is used to define functional coverage?
coverpoint
cover
covergroup
assert
What does coverpoint represent?
A sequence of events
A sampled variable or expression
A testbench module
A simulation time marker
What does cross coverage measure?
Simulation speed
Assertion failures
Timing violations
Combinations of multiple coverpoints
Which type of bin is automatically created by the simulator?
explicit
illegal
default
ignore
Which bin type is used to mark invalid or undesired values?
default
cross
ignore
illegal
When is coverage data sampled in a covergroup?
During reset
When sample() is called
At every clock edge
At simulation end
Which of the following can be used inside a covergroup definition?
coverpoint
cover
initial
always
Which keyword is used to define transition bins?
bins with |->
transitions
trans bin
bins with =>
Which of the following can cause cross coverage bins to remain unhit?
Disabled covergroup
All of the above
Missing combinations in stimulus
Incorrect sampling
What does the get() method do in a mailbox?
Sends a message
Retrieves and removes a message
Deletes the mailbox
Checks mailbox size
What happens if try_get() is called on an empty mailbox?
Simulation continues
Causes a fatal error
Returns null
Blocks until a message is available
What happens if a process calls get(n) and fewer than n keys are available?
it creates the sufficient number of keys
It blocks until keys are available
It returns immediately
it throws an error
Which method allows non-blocking retrieval from a mailbox?
sample()
try_get()
peek()
get()
Which of the following is true about peek() in mailboxes?
It blocks if mailbox is empty
It removes the message
It reads without removing
It deletes the mailbox
Which of the following statements about covergroup is true?
It can only track one variable
It cannot be used with assertions
It is mandatory for all simulations
It is used for functional coverage
What does the sample() method do in the context of a covergroup?
It triggers the covergroup to record data
It displays the coverage report
It retrieves the last sampled value
It resets the covergroup
Which of the following is a valid way to define a covergroup in SystemVerilog?
cover my_group { coverpoint a; }
covergroup my_group; coverpoint a; endgroup;
group my_group { coverpoint a; }
covergroup my_group { coverpoint a; }
Two threads call sem.get(1) simultaneously. What happens?
One thread blocks
Simulation fails
Semaphore resets
Both threads proceed
You define a cross coverage: "cross mode, enable;" After simulation, some cross bins are unhit. What’s the best explanation?
mode is constant
enable is never high
Cross coverage is disabled
Certain combinations never occur
You define a covergroup but forget to call sample(). What happens?
All bins are ignored
Coverage is collected automatically
Coverage report shows zero hits
Simulation fails
You define a covergroup to track values of a 2-bit signal: "covergroup cg @(posedge clk); coverpoint mode; endgroup" After simulation, bin[2] is never hit. What’s the best debugging step?
Check if mode is randomized
Replace coverpoint with assert
Use disable iff
Add assert(mode!=2)
In SystemVerilog, which statement repeats code a fixed number of times?
repeat
while
do...while
forever
Which loop guarantees at least one execution of the loop body?
do...while
while
for
repeat
Which SystemVerilog loop is typically used when the number of iterations is known beforehand?
do...while
while
forever
for
Which control-flow statement in SystemVerilog selects a branch based on a single expression's value?
repeat
if-else
case
fork-join
In a case statement, what does default: do?
Matches any value not matched by other branches
Is only used in casez statements
Forces simulation to stop
Causes syntax error if not last item
What is the difference between unique and unique0 on an if?
unique0 reports an error if exactly one condition true.
unique reports an error if zero or multiple conditions true; unique0 allows zero true but errors on multiple true.
They are identical.
unique allows multiple true branches; unique0 does not.
What is a priority if used for?
Ensures mutually exclusive priority encoding — later conditions checked only if earlier ones false; suppresses uniqueness checking.
Optimizes performance in simulation only
Forces parallel evaluation of conditions
Declares a sequence of concurrent statements
Which keyword helps the simulator check that if/else if branches are mutually exclusive and flags an assertion if they are not?
unique
parallel
exclusive
priority
Which of the following is TRUE about SystemVerilog function?
A function can contain timing controls like # and @.
A function must return a value (or be declared void) and cannot use timing controls.
A function can return multiple values.
A function call spawns a new thread.
What does an automatic task or function do?
Allocates local variables statically once for entire simulation.
Runs in a separate process automatically.
Prevents the use of fork inside the task.
Allocates local variables per invocation (reentrant).
Which SystemVerilog method of argument passing allows you to specify arguments by their parameter names in any order?
By position
By value only
By reference
By name (.arg(expr))
If a task has prototype task t(int a, int b); which call uses positional argument passing?
t(b:2, a:1);
t(.b(2), .a(1));
t(1, 2);
t(.a(1), .b(2));
In SystemVerilog, pass-by-position and pass-by-name differ how?
They are identical.
Position matches parameters by order; name matches parameters by explicit parameter names.
Position passes by reference; name passes by value.
Position uses .name() syntax; name uses order-only.
Which statement about fork...join in SystemVerilog is TRUE?
fork...join_none waits for the first child to finish.
fork...join is equivalent to sequential execution.
fork...join spawns parallel threads and join waits for all to complete.
fork...join_any waits for none of the children to finish.
What does fork ... join_none do?
Waits for all children to complete.
Immediately kills children.
Waits for one child only.
Returns immediately and does not wait for any child; children run concurrently.
Which SystemVerilog construct groups signal declarations and procedural code to bundle ports — used for connecting modules?
Interface
Task
Package
Class
What is a virtual interface in SystemVerilog?
An interface that is synthesized differently.
A purely simulation-only net type that cannot be used in UVM.
A handle (class-like pointer) that allows classes to reference an interface instance at runtime.
A special interface for virtual clocking only.
Which of the following statements about class member access is true?
public members are hidden from derived classes.
local class members are visible outside the class.
protected members are visible to the class and derived classes but not outside.
There is no access protection in SystemVerilog classes.
What does static mean when applied to a class variable?
Each object gets its own copy.
The variable is shared across all class instances (class-level).
The variable is read-only.
The variable is virtual.
What does $cast do in SystemVerilog?
Immediately converts integers to real numbers.
Removes references to an object.
Performs a safe dynamic cast between class handles, returning boolean success; can be used with if (!$cast(dest, src)) to test.
Performs a static compile-time cast only.
What is the scope resolution operator in SystemVerilog?
::
->
.
:
Which of these is a correct use of typedef?
typedef is not supported in SystemVerilog.
typedef class { } MyClass;
typedef int myint; — creates an alias myint for int.
typedef myint int;
What is randc?
A compile-time constant.
An alias for rand.
A qualifier that randomizes cyclically through all legal values before repeating (pseudo-random cycle).
A randomization method that produces the same value every call.
Which randomize usage allows local constraints for that invocation only?
randomize() with { ... } — the with clause supplies temporary constraints for that call.
rand_mode()
randomize() only
randomize_local()
Which keyword marks a class method as not tied to an instance (i.e., callable on the class itself)?
static
local
automatic
virtual
What does the super keyword allow you to do in a derived class?
Refer to the package-level class.
Convert object to parent type.
Access methods and fields of the parent class (call parent constructor or parent method).
Access private members only.
What is an external method in class context?
A method declared in the class with extern and defined outside.
Not supported in SystemVerilog.
A method declared with import.
A method that cannot access class members.
Which SystemVerilog construct allows multiple processes to run concurrently inside a module or initial block?
always only
fork ... join
begin ... end
function only
Which is a correct description of unique0 case?
Errors if zero matches.
Checks uniqueness and allows zero matches but errors on multiple matches.
Not supported.
Same as unique.
How do you declare a typedef for an array type?
typedef int my_arr_t[8];
int typedef my_arr_t[8];
typedefd int my_arr_t[8];
Not allowed in SystemVerilog
In SystemVerilog, what will be the outcome of the following code snippet?
Runtime error — conflicting constraints cause failure
id will be randomly chosen between 4 and 5
Compilation error — constraints cannot be modified in a with-clause
id will always be 4
For constrained random fields, how do you temporarily add a constraint for a single randomize() call?
obj.randomize_inside(x > 10);
Not possible to add temporary constraints.
obj.randomize() with { x > 10; }
obj.randomize_local({x>10});
How are pure virtual methods declared for tasks?
Tasks cannot be virtual.
pure virtual task mytask(); — analogous to functions, tasks can be declared pure virtual to force derived classes to implement them.
task mytask() pure;
Use virtual pure only for functions.
What is the default value of an uninitialized wire in SystemVerilog?
x (unknown)
z (high impedance)
0
1
Which of the following statements about wire is correct?
Wire can store values between clock edges
Wire can be assigned using always_ff blocks
Wire represents combinational logic connections
Wire supports procedural assignments
What is the default size of a reg variable in SystemVerilog?
32 bits
1 bit
16 bits
8 bits
Which statement about the logic data type is correct?
Logic can only be used in continuous assignments
Logic is deprecated in SystemVerilog
Logic can only be used in procedural assignments
Logic can be used in both continuous and procedural assignments
What is the size of a shortint data type in SystemVerilog?
8 bits
32 bits
64 bits
16 bits
What is the precision of shortreal data type?
128-bit quad precision
32-bit single precision
16-bit half precision
64-bit double precision
Which statement about real data types is correct?
Real variables can be used in sensitivity lists
Real variables are 2-state variables
Real variables are 4-state variables
Real variables can store X and Z values
How are strings stored internally in SystemVerilog?
As unpacked arrays of characters
As dynamic arrays of bytes
As packed arrays of bits
As fixed-size character arrays
What happens when you assign a shorter string to a longer string variable?
The string is truncated
Compilation error occurs
The string is padded with null characters
The string variable resizes automatically
When is the void data type typically used in SystemVerilog?
For function return types that return nothing
For parameter declarations
For array indexing
For variable declarations
Which of the following is a valid use of void?
void my_var;
function void display_msg();
parameter void PARAM = 5;
void array[10];
What is the default value of the first enumerated constant if not explicitly specified?
1
X
Z
0
Which syntax correctly defines an enumerated type with typedef?
typedef enum {RED, GREEN, BLUE} color_t;
enum color_t {RED, GREEN, BLUE} typedef;
enum typedef {RED, GREEN, BLUE} color_t;
typedef {RED, GREEN, BLUE} enum color_t;
How do you declare a dynamic array in SystemVerilog?
int arr[];
int arr[10];
int arr[*];
int arr[$];
Which array type uses a hash table for storage?
Dynamic array
Associative array
Fixed array
Queue
What symbol is used to declare a queue in SystemVerilog?
[#]
[]
[*]
[$]
Which method adds an element to the front of a queue?
insert()
push_front()
add()
push_back()
Which operator is used for non-blocking assignments?
==
<=
=
===
When should non-blocking assignments be used?
In sequential logic
In function definitions
In continuous assignments
In combinational logic
What is the difference between packed and unpacked structures?
Packed structures use more memory
Packed structures are slower
There is no difference
Packed structures are stored as contiguous bits
Which keyword is used to create a packed structure?
struct packed
packed struct
pack struct
struct
What is the key characteristic of a union in SystemVerilog?
Members must be of the same data type
All members have separate memory locations
All members share the same memory location
Members are accessed sequentially
Which syntax correctly declares a union?
union struct {int a; bit[31:0] b;} my_union;
packed union {int a; bit[31:0] b;} my_union;
struct union {int a; bit[31:0] b;} my_union;
union {int a; bit[31:0] b;} my_union;
Which loop construct is specifically designed for arrays and queues?
do-while
while
foreach
for
What is the purpose of the 'initial' block in SystemVerilog?
To create a testbench
To initialize variables at simulation start
To define a module
To define a clock signal
Which array method returns a new array with elements sorted in ascending order?
sort()
shuffle()
reverse()
rsort()
The method rsort() in SystemVerilog is used to:
Shuffle the array randomly
Rotate the array by one position
Sort the array in descending order
Reverse the array in place
Which method is used to randomize the order of array elements?
reverse()
sort()
rsort()
shuffle()
If an array is [1, 2, 3, 4], what will reverse() return?
[2, 1, 4, 3]
[3, 4, 1, 2]
[4, 3, 2, 1]
[1, 2, 3, 4]
Which ordering method modifies the array elements in place rather than returning a new array?
rsort()
All of the above
sort()
reverse()
Given the enum: typedef enum {IDLE=2, RUN=5, STOP=9} state_t; state_t s = RUN; What will s.next() return?
9
2
IDLE
STOP
Consider: typedef enum {RED=1, GREEN=2, BLUE=3} color_t; color_t c = RED; What is the result of $display("%0d", c.num());?
2
3
1
4
If an enum is declared as: typedef enum {A=1, B=4, C=7} enum_t; What will enum_t.first() and enum_t.last() return?
1 and 7
B and C
A and C
Undefined
Which string method returns the length of a string?
size()
find()
substr()
len()
