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DE End Term Quiz

Total questions: 95

Worksheet time: 2hrs 34mins

Name
Class
Date
1.

The internal circuitry of the 555 timer circuit consists of __________, an RS flip-flop, a transistor switch, an output buffer amplifier, and a voltage divider.

a)

a comparator

b)

voltage divider

c)

two comparators

d)

a peak detector

2.

What is the function of the comparators in the 555 timer circuits?

a)

to compare the output voltage to the internal voltage divider

b)

to compare the input voltage to the internal voltage divider

c)

to compare the output voltage to the external voltage divider

d)

to compare the input voltage to the external voltage divider

3.
What does the discharge transistor do in the 555 timer circuit?
a)
Charge the external capacitor to stop the timing
b)
Charge the external capacitor to start the timing over again
c)
Discharge the external capacitor to stop the timing
d)
Discharge the external capacitor to start the timing over again
4.

What is the difference between an astable multivibrator and a monostable vibrator?

a)

The astable is free running

b)

The astable needs to be clocked

c)

The monostable is free running

d)

None of the above

5.

What is the output of an astable circuit?

a)

constantly switches between two states

b)

is low until a trigger is received

c)

is high until a trigger is received

d)

floats until triggered

6.

How many stable states are available in an Astable Multivibrator?

a)

Nil

b)

1

c)

2

d)

3

7.

An astable multivibrator requires

a)

balanced time constant

b)

a pair of matched transistors

c)

no input signal

d)

dual JK flip flop

8.

Which mode of operation is used when a 555 timer chip has two external resistors and an external capacitor?

a)

Monostable

b)

Pulse Stretching

c)

Schmitt triggering

d)

Astable

9.

How many stable states are available in a Monostable Multivibrator?

a)

Nil

b)

1

c)

2

d)

3

10.
With most monostable multivibrators, what is the Q output when no input trigger has occurred?
a)
Low
b)
5V
c)
SET
d)
HIGH
11.

What is another name for a bistable multivibrator?

a)

an ON-OFF Switch

b)

an Oscillator

c)

a Flip-flop

d)

none

12.

A retriggerable one-shot has a pulse of 10 ms. Three milliseconds after being triggered, another trigger pulse is applied. The resulting output pulse will be ______ ms.

a)

3

b)

7

c)

10

d)

13

13.

Which of the following is NOT a characteristic of a retriggerable monostable multivibrator?

a)

It is a dual multivibrator

b)

It has an active high reset, which terminates all timing functions

c)

It has no internal timing resistor

d)

None of the above

14.

Which of the following is NOT an application of an Astable Multivibrator?

a)

Frequency Divider

b)

Frequency Shift Keying Generator

c)

Flasher Circuit

d)

Voltage Controlled Oscillator

15.

Which of the following is NOT an application of a Monostable Multivibrator?

a)

Frequency Divider

b)

Missing Pulse Detector

c)

PWM

d)

Voltage Controlled Oscillator

16.

In which of the following applications is Bistable Multivibrator Mode used?

a)

PPM

b)

PWM

c)

Ramp Generator

d)

Flip-flops

17.

Why are latches called memory devices?

a)

It has the capability to store 8 bits of data

b)

It can store a single bit of data

c)

It has internal memory of 4 bits

d)

None of the above

18.

Which of the following is NOT an application of a Combinational Circuit?

a)

Counter Circuits

b)

Latch Circuits

c)

Encoder Circuit

d)

Shift Register Circuits

19.
In a combinational circuit, the output at any time depends only on the _______ at that time.
a)
past output values
b)
intermediate values
c)
present input values
d)
clock pulses
20.

In a sequential circuit, the output at any time depends on both the present input values and the past output values.

a)

past output values

b)

intermediate values

c)

both past output and present input

d)

present input values

21.

What does the triangle on the clock input of any Flip-Flop mean?

a)

Level Enabled

b)

Edge-triggered

c)

Both

d)

None

22.

Why does a latch have two stable states?

a)

a latch works on the principle of bistable multivibrator

b)

a latch works on the principle of monostable multivibrator

c)

a latch works on the principle of astable multivibrator

d)

a latch works on the principle of oscillator

23.

When an active high is applied to the Set line of an SR latch, then

a)

Q' output goes HIGH

b)

None

c)

Q output goes LOW

d)

Q output goes LOW

24.
When both inputs of SR latches are low, the latch is in ___________ condition.
a)
Set
b)
No change
c)
Reset
d)
Invalid
25.

What is the full form of SR latch?

a)

SET RESET

b)

SET READY

c)

SET RESTART

d)

START RESET

26.

When is the Flip-Flop said to be transparent?

a)

When the Q output is opposite the input

b)

When the output follows the input

c)

When you can see through the IC packaging

d)

None

27.

If both inputs of an SR Flip-Flop are low, what will happen when the clock goes high?

a)

An invalid state will exist

b)

No change will occur in the output

c)

The output will toggle

d)

The output will reset

28.

Which one of the following is an application of an SR flip-flop?

a)

transition pulse generator

b)

astable oscillator

c)

racer

d)

switch debouncer

29.

One disadvantage of the SR flip-flop is

a)

It has no enable input

b)

It has a RACE condition

c)

It has no clock input

d)

It has only a single input

30.

Which of the following is not correct for the D Flip-Flop?

a)

The output toggles if one of the inputs is held high

b)

Q output follows the input D when the enable is high

c)

Only one of the inputs can be high at a time

d)

The output complement follows the input when enabled

31.

What is the output condition of a JK Flip Flop when the inputs J = 0 and K = 0?

a)

Set

b)

Reset

c)

Toggle

d)

No change

32.

Which of the following is not generally associated with flip-flops?

a)

Hold Time

b)

Propagation Delay Time

c)

Interval Time

d)

Setup Time

33.

Which of the following is an ADVANTAGE of an Asynchronous Counter Circuit?

a)

High Propagation Delay

b)

Produces Decoding Error

c)

Prone to Glitches

d)

Simple Circuit Design

34.

Which of the following is the alternative name for a 4-bit Binary Counter?

a)

MOD-10 Counter

b)

MOD-6 Counter

c)

MOD-16 Counter

d)

MOD-4 Counter

35.
The modulus of a counter is
a)
the number of flip-flops
b)
the actual number of states in its sequence
c)
the number of times it recycles in a second
d)
the number of logic gates used
36.

A decade counter with a count from zero (0000) to nine (1001) is known as

a)

an ASCII counter

b)

a binary counter

c)

a BCD counter

d)

an octal counter

37.

Which of the following is NOT an alternate name for a BCD Counter?

a)

4-bit Binary Counter

b)

Decade Counter

c)

Divide by 10 Counter

d)

Modulus of 10 Counter

38.
Which of the following is a valid state in an 8421 BCD counter?
a)
1010
b)
1011
c)
1111
d)
1000
39.
A 3-bit binary counter has a maximum modulus of
a)
3
b)
6
c)
8
d)
16
40.
A 5-bit binary counter has a maximum modulus of
a)
5
b)
8
c)
16
d)
32
41.
A modulus-12 counter must have
a)
12 flip-flops
b)
3 flip-flops
c)
4 flip-flops
d)
synchronous clocking
42.

A 4-bit ripple counter consists of flip-flops that each have a propagation delay from clock to Q output of 12 ns. For the counter to recycle from 1111 to 0000, it takes a total propagation delay of _______________.

a)

12 ns

b)

24 ns

c)

36 ns

d)

48 ns

43.

Which of the following ICs is the synchronous, presettable, 4-bit binary counter?

a)

IC 7490

b)

IC 7493

c)

IC 74160

d)

IC 74163

44.

A 4-bit binary up/down counter is in the binary state of zero. The next state in the DOWN counter mode is ___________.

a)

(0001)2

b)

(1111)2

c)

(1101)2

d)

(1110)2

45.
Three cascaded modulus-10 counters have an overall modulus of
a)
30
b)
100
c)
1000
d)
10000
46.

Which of the following MOD counters is widely used in digital clocks?

a)

MOD-5

b)

MOD-9

c)

MOD-10

d)

MOD-30

47.

Which type of counter or shift register is used in an automatic parking control circuit?

a)

Up-Down Counter

b)

Bidirectional Shift Register

c)

Universal Shift Register

d)

Ring Counter

48.

Which of the following types of shift registers is similar to the multiplexing technique?

a)

SISO

b)

SIPO

c)

PISO

d)

PIPO

49.

The output frequency of a single flip-flop will be ________ of the input frequency of the flip-flop.

a)

divide by 2

b)

divide by 4

c)

divide by 8

d)

divide by 16

50.
To enter a byte of data serially into an 8-bit shift register, there must be
a)
one clock pulse
b)
two clock pulses
c)
four clock pulses
d)
eight clock pulses
51.
To parallel load a byte of data into a shift register with a synchronous load, there must be
a)
one clock pulse
b)
one clock pulse for each 1 in the data
c)
eight clock pulses
d)
one clock pulse for each 0 in the data
52.
A modulus-8 ring counter requires
a)
8 Flip-flops
b)
4 Flip-flops
c)
12 Flip-flops
d)
5 Flip-flops
53.
A modulus-8 Johnson counter requires
a)
8 Flip-flops
b)
4 Flip-flops
c)
12 Flip-flops
d)
5 Flip-flops
54.
A DAC is a
a)
digital-to-analog computer
b)
digital analysis calculator
c)
data accumulation converter
d)
digital-to-analog converter
55.
A type of Error associated with digital to analog converters (DACs) is:
a)
nonmonotonic error
b)
incorrect output codes
c)
offset error
d)
nonmonotic and offset error
56.
In troubleshooting a DAC, we check its performance characteristics, such as______________
a)
nonmonotonicity
b)
differential nonlinearity
c)
low and high gain
d)
all of the above
57.
What is gain error in a DAC
a)
missing codes
b)
error in the slope of the output staircase waveform
c)
more or less input voltage is required for the first step than what is specified
d)
None
58.
A Binary weighted digital to analog converter has an input resistor of 100kΩ. What will be current through the resistor, if the resistor is connected to a 5V Source?
a)
50μA
b)
5mA
c)
500μA
d)
50mA
59.
In a binary weighted DAC, the lowest-value resistor corresponds to
a)
the highest binary weighted input
b)
the lowest binary weighted input
c)
the first input
d)
the last input
60.
As Compared to binary weighted digital to analog DAC converter , the major advantage of the R/2R ladder digital to analog (DAC) is
a)
It only uses two different resistor values
b)
it has a fewer part of the same number of inputs
c)
Its Operation is much easier to analyse
d)
The Virtual Ground is elimated and the circuit is therefore easier to understand and troubleshoot
61.
Which term applies to the maintaining of a given signal level until the next sampling
a)
Holding
b)
Aliasing
c)
shannon frequency sampling
d)
stair-stepping
62.
In analog to digital converter (ADCs) sample - and - hold circuits are designed to
a)
Sample and hold the output of the binary counter during the conversion process
b)
stabilize the comparator threshold voltage during the comparison process
c)
stabilize the input analog signal during the conversion process
d)
sample and hold the D/A converter staircase waveform during the conversion process
63.
What is the Purpose of Sample and Hold Circuit?
a)
To keep temporary memory
b)
Tp hold a voltage constant so an ADC has time to produce an output
c)
To hold a voltage constant so a DAC has time to produce an output
d)
To hold data after multiplexer has selected an output
64.
The most common ADC seen in telecommunications based on audio signals is
a)
flash ADC
b)
successive approximation ADC
c)
sigma-delta ADC
d)
dual slope ADC
65.
Identify from the following performance parameter of ADC in which suits the definition of no. of samples per second.
a)
Aliasing
b)
Quantization Error
c)
Resolution
d)
Sampling Frequency
66.
The quantization process
a)
converts the sample-and-hold output to binary code
b)
converts a sample impulse to a level
c)
converts a sequence of binary codes to a reconstructed analog signal
d)
filters out unwanted frequencies before sampling takes place
67.
Aliasing results in
a)
oversampling
b)
undersampling
c)
guard-band formation
d)
perfect sampling
68.
What is the Primary disadvantage of the Flash analog to digital converter (ADC)?
a)
It requires the input voltage to be applied to the inputs simultaneously
b)
a long conversion time is required
c)
a large number of output lines is required to simultaneously decode the input voltage
d)
a large number of comparators is required to represent a resonable sized binary number
69.
What is the Conversion time of flash converter?
a)
20s
b)
10s
c)
1s
d)
The Conversion takes place continuously
70.
In a flash Analog to Digital convertor,the output of each comparator is connected to an input of a ______________
a)
decoder
b)
priority encoder
c)
multiplexer
d)
demultiplexer
71.
The throughput of a flash ADC is measured in
a)
displacement per second
b)
distance per second
c)
samples per minute
d)
samples per second
72.
The main advantage of the successive - approximation A/D converter over the counter - ramp A/D converter is its:
a)
more complec circuitry
b)
less complex circuitry
c)
longer conversion time
d)
shorter conversion time
73.
The ADC0808 is an example of a _____________
a)
Single -slope analog to digital converter
b)
dual slope analog to digital converter
c)
digital ramp analog to digital converter
d)
successive approximation analog to digital converter
74.
Assume that a particular IC has a supply voltage (Vcc) equal to +5 V and ICCH = 10 mA and ICCL = 23 mA. What is the power dissipation for the chip?
a)
50 mW
b)
82.5 mW
c)
115 mW
d)
165 mW
75.
Ten TTL loads per TTL driver is known as
a)
noise immunity
b)
c
c)
power dissipation
d)
propagation delay
76.
Which type of the logic family is fabricated with simple circuit?
a)
CMOS
b)
ECL
c)
I2L
d)
TTL
77.
Which of the following is the most widely employed logic family?
a)
Emitter-coupled logic
b)
Transistor-transistor logic
c)
PMOS logic family
d)
NMOS logic
78.
Which of the following functions is the basic function of TTL gate ?
a)
AND
b)
OR
c)
EX-OR
d)
NAND
79.
Which of the following is the Propogation Delay of TTL Circuits?
a)
1 s
b)
10 s
c)
1 ns
d)
1 ps
80.
The standard TTL circuits are marked as ____________ series
a)
74
b)
82
c)
80
d)
8
81.
Which of the following is the advantage of MOS gates?
a)
Low power dissipation
b)
Small size
c)
Good immunity to noise
d)
High switching speeds
82.
CMOS gates are commercially available as which of the following series?
a)
1000
b)
2000
c)
3000
d)
4000
83.
CMOS operates more reliably than TTL in a high-noise environment because of its
a)
lower noise margin
b)
input capacitance
c)
higher noise margin
d)
smaller power dissipation
84.
When the frequency of the input signal to a CMOS gate is increased, the average power dissipation
a)
decreases
b)
increases
c)
does not change
d)
decreases exponentially
85.
Why must CMOS devices be handled with care?
a)
so they don’t get dirty
b)
because they break easily
c)
because they can be damaged by static electricity discharge
d)
all of the above
86.
Which of the following logic families has the shortest propagation delay?
a)
CMOS
b)
BiCMOS
c)
ECL
d)
74SXX
87.
What is the major advantage of ECL logic?
a)
very high speed
b)
wide range of operating voltage
c)
very low cost
d)
very high power
88.
An open collector output can ________ current, but it cannot ________.
a)
sink, source current
b)
source, sink current
c)
sink, source voltage
d)
source, sink voltage
89.
Which of the following logic families provide lowest Noise Margin?
a)
CMOS
b)
ECL
c)
I2L
d)
TTL
90.
The word "interfacing" as applied to digital electronics usually means:
a)
a conditioning circuit connected between a standard TTL NAND gate and a standard TTL OR gate
b)
a circuit connected between the driver and load to condition a signal so that it is compatible with the load
c)
any gate that is a TTL operational amplifier designed to condition signals between NMOS transistors
d)
any TTL circuit that is an input buffer stage
91.
Why is a pull-up resistor needed when connecting TTL logic to CMOS logic?
a)
to increase the output LOW voltage
b)
to decrease the output LOW voltage
c)
to increase the output HIGH voltage
d)
to decrease the output HIGH voltage
92.
When is a level-shifter circuit needed in interfacing logic?
a)
A level shifter is always needed.
b)
A level shifter is never needed.
c)
when the supply voltages are the same
d)
when the supply voltages are different
93.

What is the primary function of a D Flip-Flop in digital circuits?

a)

Generate clock signals

b)

Convert analog signals to digital

c)

Count pulses

d)

Store a single bit of data

94.

In a synchronous counter, the state changes occur on the __________ edge of the clock pulse.

a)

None of the above

b)

Both rising and falling

c)

Falling

d)

Rising

95.

Which of the following is a characteristic of a Johnson counter?

a)

It requires more flip-flops than a binary counter

b)

It has a maximum modulus of 2n

c)

It can only count up

d)

It is a type of asynchronous counter

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