Boolean Expressions with NMOS and CMOS

Which of the following is the correct approach for implementing a Boolean function in CMOS?

• Use NMOS for both pull-up and pull-down networks

• Use PMOS for pull-down and NMOS for pull-up

• Use NMOS for pull-down and PMOS for pull-up (complementary logic)

• Use resistors and NMOS in series

In NMOS logic, the logic function is primarily realized through the:

• Pull-up network

• Pull-down network

• PMOS array

• Transmission gate

Which of the following Boolean expressions is directly suitable for CMOS implementation?

• SOP form

• POS form

• NAND-NAND form

• Complemented form (using DeMorgan’s theorem)

The duality principle in CMOS logic means:

• Both pull-up and pull-down use NMOS

• NMOS and PMOS networks mirror each other logically

• Only one transistor type is required

• Outputs are tri-stated

Which expression is most efficient for CMOS implementation of F = ¬[(A + B)(C + D)]?

• SOP form

• AOI form

• NOR of ANDs

• NAND of NORs

To realize the function F = A · B + C using NMOS logic, which of the following is correct?

• Series NMOS for A and B, parallel with NMOS for C

• Parallel NMOS for A and B, in series with C

• PMOS for all inputs

• Use a CMOS inverter

In CMOS logic, what ensures zero static power dissipation?

• Using high-resistance loads

• Only one of the PMOS/NMOS networks is ON at a time

• Reducing transistor count

• Using depletion-mode devices

When realizing a logic expression in CMOS, which step should be done first?

• Draw PMOS network

• Write the complemented function

• Implement truth table

• Use XOR gates

Which logic expression is best realized using CMOS AOI logic?

• F = A + B

• F = (A · B) + (C · D)

• F = A ⊕ B

• F = A + B + C

In NMOS logic, a HIGH output voltage level is degraded because:

• PMOS pulls it too strongly

• The load is a conducting NMOS transistor

• The body terminal is floating

• There is no pull-up resistor