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WorksheetsLogic Circuit Design - Comp. Viva
Total questions: 100
Worksheet time: 50mins
Name
Class
Date
1.
A bulb in the staircase has two switches, one on the ground floor and the other on the first floor. The bulb can be turned ON and also can be turned OFF by any one of the switches, irrespective of the state of the other switch. The logic of switching on the bulb resembles ______.
a)
An AND gate
b)
An OR gate
c)
An XOR gate
d)
A NAND gate
2.
The decimal value of the signed binary number 10101010 expressed in 2’s complement form will be
a)
-42.0
b)
-86.0
c)
-116.0
d)
-170.0
3.
The smallest integer that can be represented by an 8-bit number in 2’s complement form
a)
-128.0
b)
-32.0
c)
-64.0
d)
-256.0
4.
The representation of the value of a 16-bit unsigned integer X in a hexadecimal number system is BCA9. The representation of the value of X in the octal number system is
a)
571244.0
b)
736251.0
c)
571247.0
d)
136251.0
5.
Let X be the number of distinct 16-bit integers in 2’s complement representation. Let Y be the number of distinct 16-bit integers in sign-magnitude representation. THen X-Y is
a)
1.0
b)
255
c)
65535.0
d)
32767.0
6.
In IEEE 32-bit representations, the mantissa of the fraction is said to occupy ____bits.
a)
24.0
b)
23.0
c)
20.0
d)
16.0
7.
In double precision format, the size of the mantissa is _____.
a)
32 bit
b)
52 bit
c)
64 bit
d)
72 bit
8.
The hexadecimal representation of 657 of octal is
a)
D78
b)
1AF
c)
D71
d)
32F
9.
The decimal equivalent of the hexadecimal number C3B1 is
a)
12197.0
b)
32097.0
c)
52097.0
d)
50097.0
10.
The octal equivalent of hexadecimal D.C is
a)
15.6
b)
61.6
c)
15.3
d)
61.3
11.
What is the sum of hexadecimal numbers FF and BA?
a)
B9
b)
2B9
c)
1B9
d)
139.0
12.
State the respective decimal and hexadecimal equivalent of 65 in octal
a)
53,35
b)
46,65
c)
65,46
d)
35,53
13.
The hexadecimal equivalent of the decimal number 4096 is ____
a)
1000.0
b)
F100
c)
F0
d)
1F0
14.
The representation of the value of a 16-bit unsigned integer X in a hexadecimal number system is BCA9. The representation of the value of X in octal number system is
a)
571244.0
b)
736251.0
c)
571247.0
d)
136251.0
15.
In the hexadecimal number system the radix is
a)
15.0
b)
1.0
c)
8.0
d)
16.0
16.
The hexadecimal number A0 has a decimal value equivalent to
a)
80.0
b)
256.0
c)
100.0
d)
160.0
17.
How many bit changes are there between consecutive numbers in a 4-bit Gray code sequence?
a)
1.0
b)
2.0
c)
3.0
d)
4.0
18.
Which of the following is the Excess-3 code form of decimal (215)?
a)
(0101 0100 1000)
b)
(1101 1100 1010)
c)
(0101 0101 1001)
d)
(0111 0110 1100)
19.
What is the advantage of using an Excess 3 code over a binary coded decimal (BCD) code?
a)
It requires fewer bits to represent the same number of decimal digits.
b)
It is more efficient in terms of power consumption.
c)
It is less susceptible to errors.
d)
It is more versatile and can be used for a wider range of applications
20.
What is the ASCII code for the end-of-line character?
a)
10.0
b)
13.0
c)
12.0
d)
11.0
21.
The two types of ASCII are _____________ and ____________
a)
ASCII-4 and ASCII-8
b)
ASCII-8 and ASCII-16
c)
ASCII-7 and ASCII-8
d)
ASCII-4 and ASCII-16
22.
Complement of the expression A’B + CD’ is ______
a)
(A’ + B)(C’ + D)
b)
(A + B’)(C’ + D)
c)
(A’ + B)(C’ + D)
d)
(A + B’)(C + D’)
23.
Simplify Y = AB’ + (A’ + B)C.
a)
AB’ + C
b)
AB + AC
c)
A’B + AC’
d)
AB+A
24.
The boolean function A + BC is a reduced form of _________
a)
AB+BC
b)
(A + B)(A + C)
c)
A’B + AB’C
d)
(A + C)B
25.
The logical sum of two or more logical product terms is called __________
a)
SOP
b)
POS
c)
OR operation
d)
NAND operation
26.
The expression Y=AB+BC+AC shows the _________ operation
a)
EX-OR
b)
SOP
c)
POS
d)
NOR
27.
The expression Y=(A+B)(B+C)(C+A) shows the _________ operation.
a)
AND
b)
POS
c)
SOP
d)
NAND
28.
The canonical sum of product form of the function y(A,B) = A + B is __________
a)
AB + BB + A’A
b)
AB + AB’ + A’B
c)
BA + BA’ + A’B’
d)
AB’ + A’B + A’B’
29.
A variable on its own or in its complemented form is known as a __________
a)
Product Term
b)
literal
c)
sum term
d)
word
30.
Canonical form is a unique way of representing ________
a)
SOP
b)
Minterm
c)
Boolean Expressions
d)
POS
31.
There are _____________ Minterms for 3 variables (a, b, c)
a)
4
b)
2.0
c)
8.0
d)
1.0
32.
_____________ expressions can be implemented using either (1)
2-level AND-OR
logic circuits or (2) 2-level NAND logic circuits.
a)
POS
b)
Literals
c)
SOP
d)
None of the above
33.
The output of an EX-NOR gate is 1. Which input combination is correct?
a)
A = 1, B = 0
b)
A = 0, B = 1
c)
A = 0, B = 0
d)
A = 0, B’ = 1
34.
Odd parity of word can be conveniently tested by __________
a)
OR gate
b)
AND gate
c)
NAND gate
d)
XOR gate
35.
Determine the values of A, B, C, and D that make the sum term equal to zero
a)
A = 1, B = 0, C = 0, D = 0
b)
A = 1, B = 0, C = 1, D = 0
c)
A = 0, B = 1, C = 0, D = 0
d)
A = 1, B = 0, C = 1, D = 1
36.
Which of the following expressions is in the sum-of-products (SOP) form?
a)
(A + B)(C + D)
b)
(A)B(CD)
c)
AB(CD)
d)
AB + CD
37.
The inverter can be produced with how many NAND gates
a)
1.0
b)
2.0
c)
3.0
d)
4.0
38.
What is the primary function of a multiplexer in digital systems?
a)
To perform arithmetic operations
b)
To store data temporarily
c)
To store data temporarily
d)
To generate clock signals
39.
. Which of the following statements about multiplexers is true?
a)
Multiplexers have multiple output lines
b)
Multiplexers have multiple input lines
c)
Multiplexers are used for analog signal processing
d)
Multiplexers have a negative feedback configuration
40.
What is the number of select lines required for an 8-to-1 multiplexer?
a)
2.0
b)
3.0
c)
4.0
d)
8.0
41.
In a multiplexer, which input line is selected based on the select lines?
a)
The input line with the highest voltage
b)
The input line with the lowest voltage
c)
The input line specified by the select lines
d)
All input lines are selected simultaneously
42.
What is the purpose of a demultiplexer in digital systems?
a)
To perform logical AND operations
b)
To decode binary numbers
c)
To combine multiple signals into one
d)
To route a single input to multiple outputs
43.
What is the primary function of a demultiplexer in digital systems?
a)
To perform logical AND operations
b)
To decode binary numbers
c)
To combine multiple signals into one
d)
To route a single input to multiple outputs
44.
Which of the following statements about demultiplexers is true?
a)
Demultiplexers have multiple output lines
b)
Demultiplexers have multiple input lines
c)
Demultiplexers are used for analog signal processing
d)
Demultiplexers have a positive feedback configuration
45.
What is the number of select lines required for a 1-to-8 demultiplexer?
a)
1.0
b)
2.0
c)
3.0
d)
8.0
46.
In a demultiplexer, which output line is activated based on the select lines?
a)
The output line with the highest voltage
b)
The output line with the lowest voltage
c)
The output line specified by the select lines
d)
All output lines are activated simultaneously
47.
What is the purpose of a multiplexer in combination with a demultiplexer?
a)
To perform logical OR operations
b)
To encode binary numbers
c)
To combine multiple signals into one
d)
To route multiple inputs to multiple outputs
48.
What is the primary function of an encoder in digital systems?
a)
To perform logical AND operations
b)
To decode binary numbers
c)
To convert analog signals to digital
d)
To convert digital signals to analog
49.
Which of the following statements about encoders is true?
a)
Encoders have multiple output lines
b)
Encoders have multiple input lines
c)
Encoders are used for analog signal processing
d)
Encoders have a positive feedback configuration
50.
What is the number of output lines in a 4-to-2 encoder?
a)
1.0
b)
2.0
c)
3.0
d)
4.0
51.
. In an encoder, which output line is activated based on the input lines?
a)
The output line with the highest voltage
b)
The output line with the lowest voltage
c)
The output line specified by the input lines
d)
All output lines are activated simultaneously
52.
What is the purpose of a decoder in combination with an encoder?
a)
To perform logical OR operations
b)
To decode binary numbers
c)
To convert digital signals to analog
d)
To combine multiple signals into one
53.
What is the primary function of a decoder in digital systems?
a)
To perform logical AND operations
b)
To encode binary numbers
c)
To convert analog signals to digital
d)
To convert digital signals to analog
54.
Which of the following statements about decoders is true?
a)
) Decoders have multiple output lines
b)
Decoders have multiple input lines
c)
Decoders are used for analog signal processing
d)
Decoders have a positive feedback configuration
55.
Transformation between parallel and serial port is done with help
of
a)
Flip Flop
b)
Logic circuits
c)
Shift registers
d)
None of the above
56.
Serial port is used to connect basically ____ and processor
a)
I/O devices
b)
Speakers
c)
Printer
d)
Monitor
57.
Considering a combinational function with x,y,a,b where x,a,b are
input and y is output
F(a,y,a,b)
{
If(a is 1)
y=a; else
y=b;
}
Which of the following digital logic block is most suitable
for implementing this function
a)
Full adder
b)
Priority encoder
c)
Flip Flop
d)
Multiplexer
58.
What does the "T" stand for in a T flip-flop?
a)
Toggle
b)
Trigger
c)
Time
d)
Transistor
59.
Which flip-flop type is used to divide a clock signal by 2?
a)
D flip-flop
b)
SR flip-flop
c)
T flip-flop
d)
JK flip-flop
60.
How many stable states does a T flip-flop have?
a)
1.0
b)
2.0
c)
3.0
d)
4.0
61.
Which logic gate is equivalent to an SR flip-flop?
a)
) AND gate
b)
OR gate
c)
XOR gate
d)
NAND gate
62.
Which flip-flop type is widely used for counters and frequency dividers?
a)
D flip-flop
b)
SR flip-flop
c)
T flip-flop
d)
T flip-flop
63.
How many input combinations does a D flip-flop have?
a)
1.0
b)
2.0
c)
3.0
d)
4.0
64.
What is the basic function of a CMOS inverter circuit?
a)
Voltage amplification
b)
Current amplification
c)
Logic inversion
d)
Frequency modulation
65.
Which two types of transistors are used in a CMOS inverter?
a)
PNP and NPN
b)
P-channel and N-channel
c)
Bipolar and MOS
d)
JFET and IGBT
66.
In a CMOS inverter circuit, the input signal is applied to which transistor?
a)
P-channel
b)
N-channel
c)
Both transistors simultaneously
d)
Neither transistor
67.
What is the output of a CMOS inverter when the input is high?
a)
High
b)
Low
c)
Floating
d)
Indeterminate
68.
What is the primary advantage of CMOS inverters compared to other types of logic gates?
a)
Lower power consumption
b)
Higher speed
c)
Greater noise immunity
d)
Smaller size
69.
Which factor determines the switching speed of a CMOS inverter?
a)
Supply voltage
b)
Transistor size
c)
Ambient temperature
d)
Input voltage level
70.
What is the typical output voltage levels of a CMOS inverter?
a)
VDD and VSS
b)
VDD and GND
c)
VDD and VCC
d)
VCC and GND
71.
Which logic state represents a logic "1" in a CMOS inverter?
a)
High voltage (VDD)
b)
Low voltage (VSS)
c)
Transition region
d)
Undefined voltage
72.
The output of a T flip-flop toggles when:
a)
T is HIGH
b)
T is LOW
c)
Both T and clock signals are HIGH
d)
Both T and clock signals are LOW
73.
The setup time of a flip-flop is defined as:
a)
the maximum time the input must be stable before the clock edge
b)
the minimum time the input must be stable before the clock edge
c)
None
d)
the minimum time the input must be stable after the clock edge
74.
Which of the following is a characteristic of an edge-triggered flip-flop?
a)
It changes output asynchronously
b)
It changes output only on the positive edge of the clock signal
c)
It changes output only on the negative edge of the clock signal
d)
It changes output on both the positive and negative edges of the clock signal
75.
The input equations of a J-K flip-flop are J = 0 and K = 1. What will be the output?
a)
Q = 0, Q' = 1
b)
Q = 1, Q' = 0
c)
Q = 1, Q' = 1
d)
Q = 0, Q' = 0
76.
A counter that counts in the sequence 0, 1, 2, 3, 0, 1, 2, 3 is known as a:
a)
Up counter
b)
Down counter
c)
Modulo-4 counter
d)
Ring counter
77.
Which type of flip-flop has the same input connected to both the S and R inputs?
a)
SR flip-flop
b)
JK flip-flop
c)
D flip-flop
d)
T flip-flop
78.
.How is a D flip-flop represented in Verilog?
a)
always @(posedge clk) d = q;
b)
always @(posedge clk) q = d;
c)
always @(posedge clk) q <= d;
d)
always @(posedge clk) q = ~d
79.
Which application benefits from the use of Gray code in order to minimize errors during transitions?
a)
Digital-to-analog converters (DACs)
b)
Frequency modulation (FM)
c)
Communication channels
d)
Magnetic tape storage
80.
Minimize the following expression using k-Map Y = ∑m (0,1,5,9,13,14,15) + d (3,4,7,10,11)
a)
D + (A ⊙ C)
b)
C + (A ⊙ D)
c)
D + (A̅C̅+ AB)
d)
D + AC + A̅C
81.
Product-of-Sums expressions can be implemented using
a)
2-level OR-AND logic circuits
b)
2-level NOR logic circuits
c)
BOTH
d)
NONE
82.
Which among the given expressions is the Product of Sum form?
a)
(b+c)(a+b)
b)
ac-bd
c)
ab+cd
d)
ab(cd)
83.
Which Verilog code represents the implementation of an AND gate?
a)
assign Z = A | B;
b)
assign Z = A ^ B;
c)
assign Z = A & B;
d)
assign Z = ~A;
84.
If VILmax is 0.8V, VOLmax is 0.33V then the value of NML is equal to __________________?
a)
0.7 V
b)
2.3 V
c)
0.1 V
d)
0.47 V
85.
If VOHmin is 4.3V, VIHmin is 2.0V then the value of NMH is equal to __________________?
a)
0.7 V
b)
2.3 V
c)
0.4 V
d)
6 V
86.
Which one of the following is used in high-speed operation?
a)
ECL
b)
CMOS
c)
Both a and b
d)
None of the above
87.
The value of emitter coupled logic noise margin is ______________?
a)
4 V
b)
0.2 dB
c)
3 V
d)
None of the above
88.
Which two types of transistors are used in a CMOS inverter?
a)
PNP and NPN
b)
P-channel and N-channel
c)
Bipolar and MOS
d)
JFET and IGBT
89.
The Boolean expression Y = XY + ZX is in the ___________ form.
a)
Product-of-Sum
b)
Sum-of-Products
c)
Linear
d)
None of the above
90.
According to boolean law: A + 1 = ?
a)
1.0
b)
A
c)
A'
d)
0
91.
The involution of A is equal to ________
a)
A
b)
A'
c)
1.0
92.
A(A + B) = ?
a)
AB
b)
1.0
c)
(1+AB)
d)
A
93.
Which of the following model is used to show how data flows
through a sequence of processing steps
a)
Objective models
b)
System mod
c)
Semantic data models
d)
Data flow model
94.
Which of the following identifies data flow in motion
a)
Circle
b)
Arrow
c)
Open ended box
d)
Square
95.
The code written in a Verilog test bench is ___
a)
Synthesizable
b)
Non-synthesizable
c)
Implementable
d)
None of the above
96.
What is the difference between combinational logic and sequential logic?
a)
Combinational circuits are not triggered by timing pulses, sequential circuits are triggered by timing pulses
b)
Combinational and sequential circuits are both triggered by timing pulses
c)
Neither circuit is triggered by timing pulses.
97.
If the inputs to a full adder are A=1, B=0, CIN=1 what will be the logic states on the outputs S and COUT?
a)
S = 0, COUT= 0
b)
S = 0, COUT= 1
c)
S = 1, COUT= 0
d)
S = 1, COUT= 1
98.
Which of the following is the fastest, smallest, and cheapest per unit to implement a given complex circuit in large volume?
a)
FPGA
b)
ASIC
c)
PLA
d)
CPLD
99.
How many flip-flops are required to design MOD-32 counter?
a)
6
b)
3
c)
45
d)
5
100.
Combinational logic is implemented on FPGAs using __.
a)
Robotic Arm
b)
Look Up Tables (LUTs)
c)
Microcontrollers (uCs)
d)
Multiplexers (MUXs)
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