WorksheetsMICROPROCESSOR
Total questions: 70
Worksheet time: 35mins
Name
Class
Date
1.
number of gates per packages in level of integration.
SSI
a)
a. 3
b)
b. 4
c)
c. 5
d)
q
2.
number of gates per packages in level of integration.
MSI
a)
a. 3
b)
b. 4
c)
c. 5
3.
number of gates per packages in level of integration.
LSI
a)
a. 100-100,000
b)
b. 4
c)
c. 5
d)
d.30-100
4.
number of gates per packages in level of integration.
VLSI
a)
a. 100-100,000
b)
b. >100,000
c)
c. 5
d)
d.30-100
5.
Also known as "chip" or "microchip". Is a device that integrates both active components (transistors, diodes, etc.)
a)
a. integrated circuit
b)
b. electronic circuit
c)
c. open circuit
d)
d. short circuit
6.
Advantages of integrated circuits
a)
a. Drastic reduction in size and weight
b)
b. Lower cost, large increase in realibility
c)
c. both a and b
d)
d. none of the above
7.
Disadvantages of integrated circuits
a)
a. both b and c
b)
b. handle only limited amount of power, quite delicate and cannot with stand rough handling or excessive heat
c)
c. coils or inductors cannot be fabricated, IC's function at fairly low voltages
d)
d. none of the above
8.
Classification of integrated circuits
a)
a. structure
b)
b. functions
c)
c. use
d)
d. both a and b
9.
TTL
a)
a. BJT used
b)
b. educational app
c)
c. Shottky TTL (common)
d)
d. all of the above
10.
CMOS
a)
a. MOSFET used
b)
b. industrial app
c)
c. disadvantage easily affected by ESD (electro static discharge) and low power.
d)
d. all of the above
11.
The rise time is the time it takes a pulse to go from
a)
a. the base line to the maximum HIGH voltage
b)
b. 10% of the pulse amplitude to the maximum HIGH voltage
c)
c. the base line to 90% of the pulse amplitude
d)
d. 10% of the pulse amplitude to 90% of the pulse amplitude
12.
In a certain digital waveform, the period is four times the pulse width. The duty cycle is
a)
a. 0%
b)
b. 25%
c)
c. 50%
d)
d. 100%
13.
A certain gate draws 1.8uA when its output is HIGH and 3.3uA when its output is LOW. What is the average power dissipation if Vcc is 5V and the gate is operated on a 50% duty cycle?
a)
a. 14 uW
b)
b. 1.27 uW
c)
c. 12.75 uW
d)
d. 5 uW
e)
Option 5
14.
For a CMOS gate, which is the best speed-power product?
a)
a. 1.4 pJ
b)
b. 1.6 pJ
c)
c. 2.4 pJ
d)
d. 3.3 pJ
15.
Which is not part of emitter-coupled logic (ECL)?
a)
a. Differential Amplifier
b)
b. Bias Circuit
c)
c. Emitter-follower circuit
d)
d. Totem-pole circuit
16.
BiCMOS
a)
a. Has an improve speed-power-density performance over TTL.
b)
b. Bias Circuit
c)
c. Emitter-follower circuit
d)
d. Totem-pole circuit
17.
MICROPROCESSOR UNIT
a)
a. Has an improve speed-power-density performance over TTL.
b)
b. MPU
c)
c. MCU
d)
d. Totem-pole circuit
18.
MICROCONTOLLER UNIT
a)
a. Has an improve speed-power-density performance over TTL.
b)
b. MPU
c)
c. MCU
d)
d. Totem-pole circuit
19.
Is an electronic machine that automatically process data by the use of digital techniques.
a)
a. Computer
b)
b. MPU
c)
c. MCU
d)
d. Totem-pole circuit
20.
Two major applications of computer
a)
a. Scientific and Engineering Applications
b)
b. General Commercial Applications
c)
c. both a and b
d)
d. None of the above
21.
CHARACTER OF COMPUTER
a)
a. Automatic -no human intervention
b)
b. Programmable-used stored instruction
c)
c. Electronic- no moving device-SSD (SOLID -STATE DEVICE) and Digital 1'S AD 0'S
d)
d. All of the above
22.
Memory speed of Access time
a)
a. time it takes to addressed the memory until data is available
b)
b. no. of Mbytes a memory can do
c)
c. Electronic- no moving device-SSD (SOLID -STATE DEVICE) and Digital 1'S AD 0'S
d)
d. All of the above
23.
Memory BANDWIDTH
a)
a. time it takes to addressed the memory until data is available
b)
b. no. of Mbytes a memory can do
c)
c. Electronic- no moving device-SSD (SOLID -STATE DEVICE) and Digital 1'S AD 0'S
d)
d. All of the above
24.
TYPES OF MEMORY
a)
a. Main/ Primary Memory- directly accessible by MPU
b)
b. REGISTER/ Processor Memory- used by MPU when computation/process is in progress
c)
c. R/W Semicon. Memory- very fast, ideal memory
d)
d. All of the above
25.
TYPES OF MAIN MEMORY
Is a non-volatile and read only
a)
a. ROM
b)
B. READ
c)
c. RAM
d)
d. All of the above
26.
TYPES OF ROM
Is a programmed upon manufacturer
a)
a. RAM
b)
b.. Masked ROM or ROM
c)
c. Computer
d)
d. All of the above
27.
TYPES OF ROM
Is a programmed by the user, but ONLY ONCE.
a)
a. RAM
b)
B. Masked ROM or ROM
c)
c. Programmable ROM (PROM) or One-Time Programming (OTP)
d)
d. All of the above
28.
TYPES OF ROM
Uses UV rays to erase WHOLE content; need to remove from ckt.
a)
a. Erasable PROM (EPROM)
b)
B. Masked ROM or ROM
c)
c. Programmable ROM (PROM) or One-Time Programming (OTP)
d)
d. All of the above
29.
TYPES OF ROM
Uses electrical signal to erase WHOLE content; no need to remove from ckt.
a)
a. Erasable PROM (EPROM)
b)
B. Electrically EFROM (EEPROM)
c)
c. Programmable ROM (PROM) or One-Time Programming (OTP)
d)
d. All of the above
30.
TYPES OF ROM
Erase portion of the content.
a)
a. Erasable PROM (EPROM)
b)
B. Electrically EFROM (EEPROM)
c)
c. Electrically Alterable PROM (EAPROM)
d)
d. All of the above
31.
It's a volatile, it can READ or WRITE
a)
a. RAM
b)
B. Electrically EFROM (EEPROM)
c)
c. Electrically Alterable PROM (EAPROM)
d)
d. All of the above
32.
TYPES OF RAM
Uses flip-flops (F/F) to store bit value
a)
a. static ram
b)
b. dynamic ram (DRAM)
c)
c. Cache Memory
d)
d. All of the above
33.
TYPES OF RAM
Is used in computer memory due to its HIGH capacity.
a)
a. static ram
b)
b. dynamic ram (DRAM)
c)
c. Cache Memory
d)
d. All of the above
34.
TYPES OF RAM
Very fast, small amount memory used to handle frequently used data/instruction.
a)
a. static ram
b)
b. dynamic ram (DRAM)
c)
c. Cache Memory
d)
d. All of the above
35.
found inside MPU
a)
a. Primary or L1 Cache
b)
b. Secondary or L2 Cache
c)
c. Cache Memory
d)
d. All of the above
36.
found between MPU and ram
a)
a. Primary or L1 Cache
b)
b. Secondary or L2 Cache
c)
c. Cache Memory
d)
d. All of the above
37.
is a "FIFO" device
a)
a. Primary or L1 Cache
b)
b. Secondary or L2 Cache
c)
c. Memory
d)
d. All of the above
38.
In general, the ______________ smallest bit size and the __________ have the largest.
a)
a. EEPROMs, Flash
b)
b. SRAM , mask ROM
c)
c. Mask ROM, SRAM
d)
d. DRAM, PROM
39.
EEPROM erase at byte level while FLASH drive erase at BLOCK level.
a)
a. TRUE
b)
b. FALSE
c)
c. SOMETIMES
d)
d. NOT AT ALL TIMES
40.
Technique used to transfer data IN/OUT the micro computer
a)
a. I/O
b)
b. LOGICAL/VIRTUAL I/O
c)
c. PHYSICAL I/O
d)
d. all of the above
41.
Uses OS (Operating system)
a)
a. I/O
b)
b. LOGICAL/VIRTUAL I/O
c)
c. PHYSICAL I/O
d)
d. all of the above
42.
No OS (Operating system); user is the one configure the I/O.
a)
a. I/O
b)
b. LOGICAL/VIRTUAL I/O
c)
c. PHYSICAL I/O
d)
d. all of the above
43.
Uses HANDSHAKING exchange of control signal jointly established comm.
a)
a. Programmed I/O
b)
b. Isolated/Standard I/O
c)
c. PHYSICAL I/O
d)
d. all of the above
44.
I/O space is separated to memory space. It uses IO/M pin of MPU.
a)
a. Programmed I/O
b)
b. Isolated/Standard I/O
c)
c. PHYSICAL I/O
d)
d. all of the above
45.
I/O space is located within the memory space.
a)
a. Programmed I/O
b)
b. Isolated/Standard I/O
c)
c. Memory-Mapped I/O (MMIO)
d)
d. all of the above
46.
device initiate I/O transfer.
a)
a. Interrupt I/O
b)
b. Isolated/Standard I/O
c)
c. Memory-Mapped I/O (MMIO)
d)
d. all of the above
47.
initiate by external device
a)
a. Interrupt I/O
b)
b. External Interrupt
c)
c. Memory-Mapped I/O (MMIO)
d)
d. all of the above
48.
pts to the next instruction to be fetched.
a)
a. Interrupt I/O
b)
b. External Interrupt
c)
c. PC (Program Counter) or IP (Instruction Pointer)
d)
d. all of the above
49.
Used when INT occurs. It's a "LIFO" device
a)
a. Interrupt I/O
b)
b. External Interrupt
c)
c. PC (Program Counter) or IP (Instruction Pointer)
d)
d. Stack Register
50.
Writing data into stacks
a)
a. Push Operation
b)
b. Pop Operation
c)
c. PC (Program Counter) or IP (Instruction Pointer)
d)
d. Stack Register
51.
Reading data from stacks
a)
a. Push Operation
b)
b. Pop Operation
c)
c. PC (Program Counter) or IP (Instruction Pointer)
d)
d. Stack Register
52.
Initiate by MPU itself, ex: division by zero, over flow, execution of illegal op-code.
a)
a. Internal Interrupt or TRAPS
b)
b. Direct Memory Access (DMA)
c)
c. PC (Program Counter) or IP (Instruction Pointer)
d)
d. Stack Register
53.
Directly accessing the RAM w/o involving the MPU.
a)
a. Internal Interrupt or TRAPS
b)
b. Direct Memory Access (DMA)
c)
c. PC (Program Counter) or IP (Instruction Pointer)
d)
d. Stack Register
54.
Size and lay-out of motherboard
a)
a. Internal Interrupt or TRAPS
b)
b. Direct Memory Access (DMA)
c)
c. Form Factor
d)
d. Stack Register
55.
Is a 4-bit MPU that ADD'S only.
a)
a. Internal Interrupt or TRAPS
b)
b. Direct Memory Access (DMA)
c)
c. Form Factor
d)
d. Intel 4004
56.
Is a large-scale digital IC device that can be programmed with series of instructions to perform specified functions on data.
a)
a. Microprocessor
b)
b. Direct Memory Access (DMA)
c)
c. Form Factor
d)
d. INTEL 4004
57.
A parallel wire used to carry electrical signal or data signal.
a)
a. Microprocessor
b)
b. BUS
c)
c. Form Factor
d)
d. INTEL 4004
58.
ELEMENTS OF MPU
Define the size of MPU
a)
a. ALU
b)
b. CU
c)
c. Form Factor
d)
d. INTEL 4004
59.
ELEMENTS OF MPU
Directs the sequence of operation
a)
a. ALU
b)
b. CU
c)
c. Form Factor
d)
d. INTEL 4004
60.
ELEMENTS OF MPU
General Purpose register Accumulator (ACC), etc.
a)
a. ALU
b)
b. CU
c)
c. Register Files
d)
d. INTEL 4004
61.
The archi behind All intels processor
a)
a. x86 Archi
b)
b. CU
c)
c. Register Files
d)
d. INTEL 4004
62.
It uses single-bus archi
a)
a. x89 Archi
b)
b. CISC (Complex Instruction Set Computer)Archi or Non-Volatile Neumann Archi
c)
c. RISC Archi or Harvard Archi
d)
d. all of the above
63.
It uses dual-bus archi
a)
a. x89 Archi
b)
b. CISC (Complex Instruction Set Computer)Archi or Non-Volatile Neumann Archi
c)
c. RISC Archi or Harvard Archi
d)
d. SOC (System on a chip)
64.
A complete package in one IC.
a)
a. x89 Archi
b)
b. CISC (Complex Instruction Set Computer)Archi or Non-Volatile Neumann Archi
c)
c. RISC Archi or Harvard Archi
d)
d. SOC (System on a chip)
65.
An indicator through the use of I and O.
a)
a. Flags
b)
b. CISC (Complex Instruction Set Computer)Archi or Non-Volatile Neumann Archi
c)
c. RISC Archi or Harvard Archi
d)
d. SOC (System on a chip)
66.
tells the MPU what to do
a)
a. Operational Code (OP-CODE)
b)
b. Operand
c)
c. High-Level Language
d)
d. Low-Level Language
67.
It can be Address, Immediate Value (Constant), Register.
a)
a. Operational Code (OP-CODE)
b)
b. Operand
c)
c. High-Level Language
d)
d. Low-Level Language
68.
English like language based on users interpretation level
a)
a. Operational Code (OP-CODE)
b)
b. Operand
c)
c. High-Level Language
d)
d. Low-Level Language
69.
Uses MNEMONICS, based on MPU-level of interpretation. Difficult to program.
a)
a. Operational Code (OP-CODE)
b)
b. Operand
c)
c. High-Level Language
d)
d. Low-Level Language
70.
The only language a computer can understand; 1's and 0's.
a)
a. Machine Language or Object Code
b)
b. Operand
c)
c. High-Level Language
d)
d. Low-Level Language
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