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WorksheetsCEA201
Total questions: 163
Worksheet time: 1hrs 23mins
What is a branch instruction?
A. The intructions that are used to divide a program into multiple subprograms
B. The intructions that have as one of its operands the address of the next instruction to be executed
C. The intructions that are used to pause the program
D. The intructions that are used to return to the beginning of the program
What is the primary role of the IO module? (choose two correct answers)
A. Its role is data transfer, it will transfer data to and from peripheral devices.
B. Its role is device communication control, it manages and controls the flow of data between the CPU and peripherals
C. Its role is data formatting and converting analog signals into digital audio data for CPU
D. Its role is protecting data from user, ensuring that sensitive information is not lost or intercepted.
Which of the following attributes do not belong to computer architecture?
A. Number of bits used to represent data types
C. Interface between the computer and peripherals
D. Techniques for addressing memory
E. The memory technology used
F. I/O mechanisms
Performs the computer's data processing functions is, ___________?
A. Arithmetic and logic unit (ALU)
B Control unit
C. CPU interconnection
D. Registers
The stored-program concept means a computer could get its instructions by reading them from memory, and a program could be set or altered by setting the values of a portion of memory.
A. True
B. False
What electronic component is used to govern operations such as fetching, decoding, and performing arithmetic operations executed by a processor?
A. Using a system clock
B. Using a quartz crystal
C. Using a analog to digital converter
D. Using a counter
Consider an expression: 1000 0000 AND 1111 1010
What is the result of this expression?
A. 1000 0000
Β. 1111 0000
C. 1001 1010
D. 1001 0101
The instruction, which adds 1 to thevalue in a memory location, has five stages: fetch opcode (four cycles), fetch operand address (three cycles), fetch operand (three cycles), add 1 to operand (three cycles), and store operand (three cycles). An interrupt sends request at beginning of fetch operand stage. How many cycles does the processor enter the interrupt processing cycle?
A. 6
B. 7
C. 8
D. 9
E 10
What is the benefit of cache memory in terms of computer performance?
A. It reduces the computer's power consumption
B. It speeds up data access and improves system performance.
C. It increases the storage capacity of the computer.
D. It serves as a backup storage for critical files.
Which of the following determines the Bus Width?
A. The clock speed of the CPU
B. The number of cores in the processor
C. The size of the motherboard
D. The number of parallel lines in the data bus
E. Number of components connected to Bus
Which method of accessing units of data is used to copy a block in main memory into cache memory?
A. Direct access
B. Random access
C. Sequential access
D. Associative
Which of the following algorithms is not typically used in cache memory replacement?
A. Least Recently Used (LRU)
B. First-In-First-Out (FIFO)
C. Least Frequently Used (LFU)
D. Round Robin (RR)
Consider a machine with a byte addressable main memory of 2^16 bytes and block size of B bytes. Assume that a direct mapped cache consisting of 32 lines is used with this machine. How many bits are there in the line field of the cache?
A 3
B. 4
C. 5
D. 6
E. 7
In terms of organization, what is the basic element of semiconductor memory?
A. Memory capacity
B. Memory block
C. Memory cell
D. Memory location
Using Hamming Code with one error corection to store an 12-bit word in memory, the stored word 111001001101 consists of 8 bits data and 4 bit bits parity check. What are the parity bits?
A. 0110
B. 0111
C. 1110
D. 0101
E. None of the mentioned
What are the key differences in the architecture of NOR and NAND flash memory?
A. NOR flash memory cells are connected in series, while NAND flash memory cells are connected in parallel
B. NOR flash memory cells are connected in parallel, while NAND flash memory cells are connected in series
C. Both NOR and NAND flash memory cells are connected in series
D. Both NOR and NAND flash memory cells are connected in parallel
E. All of the mentioned are wrong
With the hard disk data layout, the set of all the tracks in the same relative position on the platter, is called__________
A. Cylinder
B. Tracks
C. Inter-track gap
D. Sector
Which is incorrect about RAID?
A. RAID is a set of physical disk drives viewed by the operating system as a single logical drive.
B. Data are distributed across the physical drives of an array in a scheme known as striping, described subsequently.
C. RAID is only used for Windows OS
D. Redundant disk capacity is used to store parity information, which guarantees data recoverability in case of a disk failure.
In terms of data storage, what is the main distinction between a solid state drive and a magnetic disk?
A. A magnetic disk uses a spinning platter and a read/write head, while a solid state drive uses flash memory chips
B. A magnetic disk uses flash memory chips, while a solid state drive uses a spinning platter and a read/write head
C. A magnetic disk and a solid state drive both use flash memory chips, but with different interfaces
D. A magnetic disk and a solid state drive both use a spinning platter and a read/write head, but with different speeds
___________:Determine the address of the next instruction to be executed. Usually, this involves adding a fixed number to the address of the previous instruction.
A. Instruction fetch
B. Instruction operation decoding
C. Instruction address calculation
D. Operand fetch
E Operand address calculation
In which I/O technique does an I/O channel or processor manage transfer of data, thus freeing the CPU?
A. Programmed I/O
B. Interrupt-driven I/O
C. Channel I/O
D. Memory-mapped I/O
The I/O technique where the processor busy waits for an I/O operation to complete is called______
A. Programmed I/O or DMA
B. Interrupt-driven I/O
C. Direct Memory Access (DMA)
D. Programmed I/O
What is the main distinction between Interrupt-Driven I/O and Direct Memory Access (DMA)?
A. Interrupt-Driven I/O involves the CPU in every data transfer, while DMA bypasses the CPU and transfers data directly between I/O device and memory
B. Interrupt-Driven I/O requires special hardware and software support, while DMA does not need any additional components
C. Interrupt-Driven I/O is suitable for small and frequent data transfers, while DMA is suitable for large and infrequent data transfers
D. All of the mentioned
What role does an Application Programming Interface (API) play in software development?
A. It allows program access to hardware resources using high-level language libraries
B. It defines low-level machine instructions
C. It provides a standard for binary portability
D. It manages system resources for the operating system and machine language instructions
Which state indicates that a process is currently being executed by the processor?
A. Running
B. Ready
C. NewBorn
D. Halted
Which of the following statements is incorrect about Translation Look-aside Buffer (TLB)?
A. The use of TLB eliminates the need for keeping a page table in memory
B. TLB only maintains a subset of the entries stored in the full memory-based page table
C. When there is a TLB miss the system needs to access the page table
D. A translation lookaside buffer (TLB) is a memory cache that stores the recent translations of virtual memory to physical memory
How does Boolean algebra contribute to the design of digital circuits?
A. It simplifies the implementation of desired functions
B. It helps in the analysis of economic data
C. It facilitates the design of analog circuits
D. It is primarily used for chemical engineering and physical engineering
What is the output of a NOT gate when the input is 0?
A 0
B 1
C. Undefined
D. 2
What is result logical right shift of 10110000 by 2 bit?
A. 00101100
B. 01011000
C. 01001100
D. 00110000
If you have an integer number +18 in sign magnitude representation, which is 00010010, what is the correct option for -18?
A. 00010010
B. 10010010
C. 11110010
D 01110010
Why is it essential to use symbolic representation of machine instructions?
A. It makes machine instructions more human-readable and understandable
B. It reduces the overall complexity of computer systems and user programs
C. It minimizes the need for memory storage for the user programs
D. It enables fastest execution of high level language instructions
The hardware mechanism that allows a device to notify the CPU is called______
A. polling
B. interrupt
C. driver
D. controlling
In the context of addressing modes with both indirect addressing and indexing, what is postindexing?
A. Indexing is performed after the indirection
B. Indexing is performed before the indirection
C. Both indexing and indirection are avoided
D. Indexing and indirection occur simultaneously
EEPROM is read-mostly-memory and volatile
A. True
B. False
Which architectural concept involves replicating register banks to facilitate the sharing of pipeline resources among multiple threads?
A. Pipelining
B. Superscalar
C. Simultaneous multithreading
D. Superpipelining
Steps for executing a machine instruction are concerned, given an assembly code: ADD EAX, V. What step will access the variable V?
A. The fetch data step.
B. The fetch instruction step.
C. The process data step.
D. The interpret instruction step
The PC, IR, MAR, MBR registers belong to which of the following groups?
A. Control and Status Registers
B. User-Visible Registers
C. General Registers
D. Handle Registers
What is the significance of the program counter (PC) in the fetch phase of the instruction cycle?
A. The program counter (PC) is not used in the fetch phase, and its role is limited to tracking the number of instructions executed by the CPU
B. The program counter (PC) in the fetch phase holds the memory address of the next instruction to be fetched and executed
C. The program counter (PC) is responsible for executing instructions and has no specific role during the fetch phase
D. The program counter (PC) is only relevant in multi-core processors and does not contribute to the fetch phase of the instruction cycle in single-core systems
In the context of instruction execution, how is a product on an assembly line conceptually similar to an instruction in a pipeline?
A. Both undergo multiple stages of production
B. Both are executed in a single clock cycle
C. Both follow a linear sequence of tasks
D. Both are processed by the control unit
In various statement types in a high-level programming language, what is not the most common statement?
A GOTO statement
B. IF statement
C. CLOOP statement
D. CALL procedure statement.
In the concept of Register Windows, how many register groups are there?
A 4
B. 3
C. 2
D. No distinction
What is the main benefit of using RISC over CISC?
A. RISC has more instructions and addressing modes than CISC
B. RISC has faster instruction execution and simpler instruction decoding than CISC
C. RISC has variable-length instruction formats and direct memory access than CISC
D. RISC has more registers and pipelines than CISC
In SuperScalar computer architecture, the primary goal of utilizing multiple processors concurrently is to
A. Increase processing speed by increasing CPU frequency
B. Improve performance by executing more than one instruction per machine cycle.
C. Reduce the size of the CPU to conserve energy.
D. Enhance computational power by increasing the number of CPU cores.
To enhance performance in a superscalar processor, which method(s) should we apply?
A. Duplication of resources
B. Out-of-order issue.
C. Renaming registers
D. All of the mentioned.
How many common classifications of parallel systems are there as proposed by Flynn?
A 2
B 3
C. 4
D. 5
Which write technique in which all write operations are made to main memory as well as to the cache, ensuring that main memory is always valid.
A. Write through
B. Write back
C. Write around
D. No write allocate
How does multithreading improve the performance of a processor?
A. It increases the instruction-level parallelism by issuing multiple instructions from different threads in the same cycle
B. It increases the thread-level parallelism by executing multiple threads on different cores or processors
C. It increases the utilization of the processor resources by hiding the latency of long-latency events such as cache misses or branch mispredictions
D. All of the mentioned
Follow the Amdahl's law for multiprocessors, if only 10% of the code is inherently serial (f = 0.9), running the program on a multicore system with 4 processors, a performance gain (speedup factor) would be_____
A. 307%
B. 297%
C. 317%
D. 327%
Which cache is not a shared cache?
A. L4 cache
B. L3 cache
C. L2 cache
D. L1 cache
In the MASM, how to receive numbers from user?
A. Raw data from keyboard are string. The function sval(num-string) will convert num-string to signed number
B. Raw data from keyboard are string. The function str$(num-string) will convert num-string to signed number
C. Raw data from keyboard are string. The function chr$(num-string) will convert num-string to signed number.
D. Raw data from keyboard are string. The function chr$(num-string) will convert num-string to unsigned number.
What are the most basic functions of an I/O module?
A. Control and timing, processor communication, device communication, data buffering, error detection.
B. Control and timing, processor communication, data buffering, error detection, writing data to memory
C. Control and timing, processor communication, device communication, data buffering, blocking device.
D. Control and timing, processor communication, device communication, error detection, data processing.
In isolated I/O__________
A. The I/O devices and the memory share the same address space
B. The I/O devices have a separate address space from memory
C. The memory and I/O devices have an associated address space
D. A part of the memory is specifically set aside for the I/O operation
Which component defines the system call interface to the operating system and facilitates binary portability?
A Application Binary Interface
B. Application Programming Interface
C. Instruction Set Architecture
D. Central Processing Unit
What is the initial state of a process when it is admitted by the high-level scheduler, but not yet ready to execute?
A. New
B. Ready
C. Running
D. Halted
Which method allows the programmer to view memory as consisting of multiple address spaces and is used to map logical addresses of variable length onto physical memory?
A. Paging
B. Overlays
C. Segmentation
D. Paging with segmentation
What is the distinction between Computer Architecture and Computer Organization?
A. Computer Architecture is the way the system is structured, while Computer Organization is those attributes of a system that are visible to the user
B. Computer Architecture is those attributes of a system that are visible to the user, while Computer Organization is the way the system is structured
C. Computer Architecture and Computer Organization are the same
D. Computer Architecture is slower than Computer Organization
What is result of 10100101 xor 11001001?
A. 11101101
B. 10000001
C. 01101100
D. 10101100
Which registers can be assigned to a variety of functions by the programmer?
A. Data registers
B. General purpose registers
C. Address registers
D. Condition codes (flags)
What is the output of Left Shift Operator << on (00011000<<2)?
A. 01100000
B. 11000000
C. 00000110
D. 00000011
Which addressing mode allows direct specification of the memory address within the instruction?
A. Direct
B. Indirect
C. Register Indirect
D. Displacement
Which of the following PDP series computers is known for its use of 12-bit instructions and a single general-purpose register, the accumulator?
A. PDP-8
B. PDP-10
C. PDP-11
D PDP-6
In modem computers, which devices among the memory types usually have the smallest capacity?
A. RAM
B. Magnetic Tape
C. Hard Disk Drive
D. Cache Memory
Which of the following statements is true for Von Neumann architecture?
A. Shared bus between the program memory and data memory
B. Separate bus between the program memory and data memory
C. External bus for program memory and data memory
D. External bus for data memory only
During the development process of the computer, which of the following statements is false?
A. The second generation uses transistors
B. The first generation uses vacuum tubes
C. The fourth generation uses integrated circuit
D. The third generation uses transistor
What is Memory Address Register (MAR)?
A. Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit.
B. Employed to hold temporarily the righthand instruction from a word in memory.
C. Contains the address in memory of the word to be written from or read into the MBR.
D. Contains the address of the next instruction pair to be fetched from memory.
In the computer, what categories do external devices include? (choose 3 correct answers)
A Human readable
B. Communication
C. Data Conversion
D. Machine readable
Consider an expression: 1000 0000 OR 1111 1010 What is the result of this expression?
A. 1000 0000
Β. 1111 1010
C. 1001 1010
0101
_________interprets the instructions in memory and causes them to be executed.
A. Registers
B. CPU interconnection
C. Arithmetic and Logic Unit (ALU)
D. I/O Modules
E. Control Unit (CU)
A set-associative cache consists of 64 lines, divided into four-line sets. 2^19-words main memory contains 4K blocks of 128 words each. How many bits are there in the tag field of the cache?
A. 5
B. 6
C. 7
D. 8
E9
How many bytes of data does each sector in the Winchester hard drive disk have?
A. 128 bytes
B. 256 bytes
C. 512 bytes
D. 1024 bytes
E. 4096 bytes
What is the main idea of using Hamming code for error correction?
A. Adding extra parity bits to the data bits such that the number of 1s in each subset of bits is even
B. Adding extra parity bits to the data bits such that the number of 1s in each subset of bits is odd
C. Adding extra parity bits to the data bits such that the parity bits form a binary number indicating the position of the error bit
D. Adding extra parity bits to the data bits such that the parity bits form a binary number indicating the number of error bits
What is correct about increasing performance and endurance?
A Hard Disk- DRAM-NAND Flash - SRAM
B. Hard Disk-NAND Flash-DRAM- SRAM
C NAND Flash - Hard Disk-SRAM-DRAM
D. Hard Disk - DRAM-SRAM - NAND Flash
Which is the correct choice for sorting in increasing speed average of memory?
A SSD Main Memory < Cache Memory < Magnetic Tape
B. Magnetic Tape < SSD < Cache Memory < Main Memory
C. Magnetic Disk SSD Main Memory < Cache Memory
D. Magnetic Disk < Magnetic Tape < Main Memory < Cache Memory
What is the primary function of the Arithmetic and Logic Unit (ALU) in a processor?
A. Perform actual computations and data processing
B. Control the movement of data and instructions
C. Act as an interface to the system bus
D. Manage the internal processor memory
How many general-purpose registers are there in the Microprocessor Register Organizations of Intel 80386-Pentium 4?
A. 8
B. 16
C. 4
D. 12
What does CISC stand for?
A. Complex Instruction Set Computer
B. Computer Instruction Set Complex
C. Complex Instruction Summarize Computer
D. Computer Instruction Summarize Complex
________there are multiple functional units, each of which is implemented as a pipeline.
A Scalar
B. Superpinelined
C. Superscalar
D. Vector
"Multiple processors share a single memory or pool of memory by means of a shared bus or other interconnection mechanism, a distinguishing feature is that the memory access time to any region of memory is approximately the same for each processor. Which concept does the statement belong to?
A. Symmetric multiprocessor (SMP)
B. Nonuniform memory access (NUMA)
C. Cluster
D. Single instruction, multiple data (SIMD)
What is the most common mapping technique used in cache memory in modern computers?
A Direct Mapping
B Fully Associative
C. Set Associative
D. None of the mentioned
Choose the most four basic functions of a computer.
A. Moving data, storing data, processing data, controlling
B. Supporting operating system, accessing hard disks, supporting network connections, supporting HDMI ports.
C. Reading disks, accessing network resources.
D. Reading data from keyboard, printing data to monitor, allowing network connections.
_______refers to the operational units and their interconnections that realize the architectural specifications.
A. Computer architecture
B. Computer function
C. Computer organization
D. Instruction set architecture.
What is the most important function of the control unit (CU)?
A. It manages the order of running instructions
B. It will read and process data from main memory
C. It directs the operation of the other CPU components.
D. It will read instructions from main memory then decoding them.
The first generation of computers used________ for digital logic elements and memory?
A. Transistor
B Integrated Circuits
C. Large-scale integration
D. Vacuum Tubes
What is false about the von Neumann architecture?
A. Data and instructions are stored in a single read-write memory
B. The contents of this memory are addressable by location, without regard to the type of data contained there.
C. Execution occurs in a sequential fashion (unless explicitly modified) from one instruction to the next.
D. Data is stored in main memory and instructions are stored in cache memory
What is the maximum addressable memory of a 32-bit microprocessor with 24-bit address?
A. 16 GB
B. 16 MB
C. 16 Gbits
D. 16 Mbits
What is the most important characteristic of the Synchronous Bus?
A. Data is transmitted at the same time
B. The occurrence of one event on a bus follows and depends on the occurrence of a previous event
C. The occurrence of events on the bus is determined by a clock
D. No common clock signal controlling operation
What is the correct order of memory access speed from fastest to slowest?
A. Registers > Cache > RAM > SSD
B. Cache Registers > RAM > SSD
C. Registers > Cache > SSD > RAM
D. Cache > Registers > SSD > RAM
E. All of the mentioned are wrong
What is the special feature of Memory Cache?
A. Allows faster access than DRAM memory
B. Memory cache is outboard storage memory
C. Allows faster access than CPU registers
D. Fixed memory - Read Only Memory
E. Has a larger capacity than HDD
In the direct mapping method from 256MB main memory with 512KB cache, what is the number of bits for the TAG element in the address?
A. 6
B. 7
C. 8
D.9
A byte addressable microprocessor has 24 bit address. What is maximum memory capacity?
A. 4 MegaByte
B. 8 MegaByte
C. 16 MegaByte
D. 32 MegaByte
In error correcting code (single ECC), how many bits are used to correct one bit in 8-bit data?
A. 4.
B. 5
C. 6
D. 7
Which RAID level uses striping technique with a minimum of 3 disks and provides fault tolerance through the use of parity bit?
A. RAID 0
B. RAID 1
C. RAID 2
D. RAID 3
In terms of performance, what is the main advantage of a solid state drive over a magnetic disk?
A. A solid state drive has faster access time, lower latency, and higher reliability
B. A solid state drive has larger capacity, lower power consumption, and lower cost
C. A solid state drive has better compatibility, longer lifespan, and higher security
D. A solid state drive has none of the mentioned advantages over a magnetic disk
Consider the expression: NOT(A + B) = ? Apply DeMorgan's Theorem to replace at "?"
A. NOTA AND NOT B
B. NOT A OR NOT B
C. NOT A AND B A OR NOT B
(1) An I/O module must recognize one unique address for each peripheral it controls. (2) I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on mainframes. The statement (1) is__________ and (2) is________
A true, false
B. true, true
C. false, true
D. false, false
What is an interrupt vector?
A. Part of memory which contains the addresses of interrupt handlers
B. A signal an I/O device sends to CPU
C. A signal an I/O software sends to CPU
D. None of the mentioned
______If the operation involves reference to an operand in memory or available via I/O, then determine the address of the operand.
A. Operand fetch
B. Data operation
C. Operand store
D. Operand address calculation
When both inputs are 1, what is the result of a NAND gate?
A. 0
B. 1
C. 2
D. Undefined
E #NA
What is result left rotate of 10110101 by 2 bit?
A 01101011
B. 10101101
C. 01101101
D. 11010110
E. 11010100
What are the most important general categories of data that machine instructions operate on?
A. Addresses, numbers, characters, and logical data
B. Text, images, and audio
C. Variables, functions, and arrays
D. Instructions, control signals, and registers
The effective address of Register indirect addressing mode is_______
A EA-R
B. EA = (R)
C. EA = (R)+A
D. EA = (R)+(A)
What is the main difference between x86 and ARM instruction formats?
A. x86 instructions are variable in length, while ARM instructions are fixed
B x86 instructions are fixed in length, while ARM instructions are variable
C. Both x86 and ARM instructions are fixed in length
D. Both x86 and ARM instructions are variable in length
What is the primary purpose of the "Fetch instruction" phase in the operation of a processor?
A. To read an instruction from memory
B. To interpret the instruction
C. To perform arithmetic operations on data
D. To write data to memory
Control and status registers are used by which entities to control the operation of the processor?
A. Privileged, operating system programs
B. Machine or assembly language programmers
C. External I/O devices
D. Main memory modules
Which of the following statement is correct in the context of Instruction Pipelining?
A. Instruction Pipelining reduces the efficiency of instruction execution by introducing delays and dependencies between instructions
B. Instruction Pipelining is only effective for specific types of instructions and has no impact on the overall efficiency of instruction execution
C. Instruction Pipelining enhances efficiency by enabling simultaneous execution of multiple instructions in different stages, boosting overall throughput
D. Instruction Pipelining improves efficiency by processing multiple instructions simultaneously, reducing execution time. However, it can face challenges like hazards, introducing delays and impacting overall performance
Which statement is incorrect about RISC and CISC architecture?
A. CISC architecture is more convenient for programmers than RISC architecture.
B. CISC architecture has more operands in a instruction compared to RISC architecture.
C. CISC architecture has a more flexible instruction set than RISC architecture.
D. CISC architecture requires more general-purpose registers than RISC architecture.
What is one of the advantages of using a register file in computer architecture?
A. Reduction in memory accesses, saving time
B More efficient use of space due to dynamic adaptation
C. Efficient handling of both local and global variables
D. Easier management of cache residency
How does pipelining in a RISC architecture handle branch instruction?
A. By using NOOP instructions inserted by the compiler or assembler
B. By eliminating branch instructions from the instruction stream
C. By executing branch instructions in a separate pipeline
D. By delaying all instructions until branch instructions are executed
What is the benefit of using a superscalar organization over a scalar organization?
A. It increases the instruction throughput and improves the performance
B. It reduces the power consumption and the heat dissipation
C. It simplifies the instruction set and the compiler design
D. All of the mentioned
E. None of the mentioned
What does the term "instruction-level parallelism" refer to in computer architecture?
A. The degree to which instructions in a program can be executed in parallel
B. The number of processor cores in a multi-core CPU with multiple resources
C. The complexity of the instruction set architecture
D. The length of an instruction cycle with high level programing lariguage
What is one advantage of Nonuniform Memory Access (NUMA) over Uniform Memory Access (UMA)?
A. NUMA provides each processor with its own local memory, reducing memory access times
B NUMA allows all processors to access the same memory location simultaneously
C. NUMA is easier to implement than UMA
D. NUMA provides limited memory capacity
Which portion of a computer consists of an ALU, a control unit, and registers, uses for fetching and executing instructions?
A. Main memory
B. CPU
C. I/O
D. System interconnection
Choose the appropriate words to fill in the corresponding blanks in the following definitions:
_______contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit.
___________specifies the address in memory of the word to be written from or read into the MBR.
____________is employed to hold temporarily the right hand instruction from a word in memory.
A MBR, MAR, IBR
B. AC, MAR, IR
C. MAR; MBR, IBR
D. AC; MBR; MAR
What is the role of the memory address register (MAR) in a computer system?
A. It holds data being transferred between memory and the processor.
B. It specifies the address in memory for the next read or write operation.
C. It performs arithmetic operations on data stored in memory.
D. It stores program instructions after they are executed.
The basic components of a computer are:
A. Main memory, CPU, I/O modules and system interconnection
B. Main memory, CPU, I/O modules and Storage device
C. Main Memory, CPU, Peripherals and Storage device
D. Main memory, CPU, I/O modules and Peripheral device
A two-way set-associative cache has lines of 16 bytes and a total size of 8 Kbytes. The 64-Mbyte main memory is byte addressable. What are the values of Tag, Set and Byte offset fields?
A. 14/8/4
B. 16/6/4
C. 12/10/4
D. 15/7/4
E 13/9/4
Consider an expression: NOT (1111 1010)
What is the result of this expression?
A 0000 1010
B. 0000 0101
C. 11110101
D. 1111 1010
How many check bits are needed for a Hamming error correction code to detect single-error correction in a 1 KByte data word?
A. 11 bits
B. 12 bits
C. 13 bits
D 14 bits
E 15 bits
The use of Hamming code on 4-bit words (M= 4) is illustrated in the below Venn diagrams. With three intersecting circles, there are seven compartments. We assign the 4 data bits to the inner compartments. The remaining compartments are filled with what are called parity bits. Each parity bit is chosen so that the total number of 1s in its circle is even. Choose the correct value of the corresponding parity bit in circles A, B, C.
A. 1; 0; 0
B. 0; 1; 0
C. 0, 0, 1
D. 1,0; 1
Using Hamming Code with one error correction to store a 12-bit word in memory, the stored word 101001011101 consists of 8 bits data and 4 bits parity check. What are the data bits?
A. 01001101
B. 10100100
C. 10101011
D. 01011101
E None of the mentioned
From a structural point of view, the external devices are controlled by________
A. Control signals
B. Peripheral device
C. I/O modules
D. Remote devices
Which of the following is a DISADVANTAGE of using programmed I/O?
A Increases system efficiency
B. Reduces CPU involvement in I/O operations
C. Requires the CPU to be constantly busy with I/O tasks
D. Increases system complexity
What is the purpose of using an API?
A. To enable application software to be ported easily to other systems that support the same API
B. To define the repertoire of machine language instructions
C. To standardize binary portability across programs
D. To manage system resources
Which of the following are the 4 basic functions of a computer?
A. Data processing; Data storage; Data movement, CPU.
B CPU; Main memory; I/O, System interconnection.
C. Control unit, ALU, Registers, CPU interconnection.
D. Data processing, Data storage, Data movement, Control.
Which of the following components was used in the first ENIAC computer?
A. Bipolar transistors
B. Field transistors
C. Vacuum tubes.
D. Semiconductor los
What is a characteristic of Many Integrated Core (MIC) chips?
A. They include only specialized cores for specific tasks.
B. They consist of homogeneous general-purpose processors on a single chip
C. They are designed to eliminate the need for GPUs in high-performance applications.
D. They have limited scalability beyond four cores per chip.
The instruction, which adds 1 to the value in a memory location, has five stages: fetch opcode (2 bus cycles), fetch operand address (2 bus cycles), fetch operand (2 bus cycles), add 1 to operand (1 bus cycle), and store operand (3 bus cycles). An interrupt sends request at beginning of fetch operand address stage. How many cycles does the processor enter the interrupt processing cycle?
A 6
B. 7
C. 8
D. 9
E. 5
Which type of interrupt is exemplified by "division by zero, attempt to execute an illegal machine instruction"?
A. Program
B. Timer
C. I/O
D. Hardware failure
Which type is not an Interconnection bus?
A Data lines
B Control lines
C. Signal lines
D. Address lines
Which kind of cache mapping maps each block of main memory into one unique line of the cache?
A. Direct mapping
B. Set associative mapping
C. Fully associative mapping
D. Direct access
Which of the following memory devices has the lowest access speed?
A ROM
B. Flash memory
C. Magnetic tape
D. HDD
E. Cache
If the address received when accessing the cache memory includes Tag, Line, Word. At that time, what mapping technique is the system using?
A. Direct mapping
B. Set-direct mapping
C. Associative mapping
D. Set-associative mapping
What is the key advantage of double-data-rate SDRAM compared to standard SDRAM?
A. It has a larger memory capacity.
B. It can send data twice per clock cycle.
C. It uses less power than SDRAM
D. It is only compatible with desktop computers.
For reads to and writes from main memory,___________ translates each virtual address into a physical address in main memory.
A MAR
B. MMU
C. Overlays
D. TLB
E. Accumulator
How many check bits are needed if the Hamming error correction code is used to detect single bit error in a 128-bit data word?
A. 6 bits
B. 7 bits
C. 8 bits
D. 9 bits
E 5 bits
Which of the following issues are peculiar to SSDs compared to HDDs?
A. Performance slows down as the device is used.
B. A certain number of writes make the flash memory unusable.
C. They are more vulnerable to physical damage.
D. They require defragmentation to maintain performance.
E. They are slower at data retrieval compared to HDDs.
Which memory has the fastest speed and smallest capacity?
A Cache
B Main memory
C. HDD
D. Magnetic Disk
Sort the following memory types in ascending order by access speed:
A. HDD-Main Memory - L2 cache -L1 cache
B. HDD-Main Memory-L1 cache - L2 cache
C. HDD-L2 cache-L1 cache Main Memory
D. Main Memory-L2 cache-L1 cache - HDD
What is the first evolutionary step in the evolution of the I/O function?
A. The I/O module is enhanced to become a processor in its own right.
B. A controller or I/O module is added, and programmed I/O without interrupts is used.
C. The CPU directly controls a peripheral device.
D. The I/O module is given direct access to memory via DMA.
E. The I/O module has a local memory of its own.
In programmed I/O, who does initialize the transfer of data?
A. I/O controller
B CPU
C. DMA controller
D. Operating system
__________Read instruction from its memory location into the processor.
A. Instruction fetch
B. Instruction operation decoding
C. Operand address calculation
D. Data operation
The ____________scheduler executes relatively infrequently and makes the coarse-grained decision of whether or not to take on a new process, and which one to take. The ____________scheduler, also known as the dispatcher, executes frequently and makes the fine-grained decision of which job to execute next.
A short-term; medium-term
B. medium-term, short-term
C. long-term, short-term
D. long-term, medium-term
If a program accesses data in a specified file, how to manage the file's properties such as disk position, file's attributes?
A. They are managed by the current operating system.
B. They are managed using variables of the running program.
C. They are stored on the hard disk.
D. They are managed by the programmer.
The decision as to which process's pending I/O request shall be handled by an available I/O device
A Medium-term scheduling
B. Short-term scheduling.
C. I/O scheduling
Which of the following is a characteristic of sequential circuits compared to combinational circuits?
A. Do not use gates
B. Output depends only on current inputs
C. Output depends on current inputs and past inputs
D. Simpler to design and implement
(R1)=01110110, (R2) = 11011111, the result of (R1) XOR (R2) is:
A. 11011011
B. 00010110
C. 10101001
D. 11001101
Given the following Karnaugh map, what is the optimal expression in the sum of product format (X' means Not X)?
A. A'B + AC'D + ACD'
B. AB+ AC + ACD'
C. AB+ AD + ACD'
D. A'B+C'D + BCD
Convert the 64 from decimal to their binary number equivalents.
A. 100000
B. 100100
C. 111000
D. 101010
In a conditional branch instruction, what happens if the specified condition is met?
A. The program counter is updated to equal the address specified in the operand.
B. The program counter increments as usual
C. The instruction is skipped
D. The program terminates.
With respect to elements of a machine instruction, what does the instruction code mean?
A. It specifies the operation to be performed.
B. It specifies data which will be processed
C. It specifies memory access.
D. It specifies an IO device.
What is the primary advantage of indirect addressing mode?
A. Faster access to operands
B. Ability to access a larger data set
C. Flexibility in data location
D. Reduced instruction size
In MASM32, which OPCODE is used to compare two values?
A COM
B. CMP
C IF ELSE
D. TEST
What is the primary purpose of index registers within the processor?
A. To manage control signals
B. To hold condition codes
C. To facilitate indexed addressing
Index registers are used for storing D. To execute arithmetic operationsprogram instructions.
Steps for executing a machine instruction are concerned, choose the most suitable statement for the role of the interpret instruction step.
A. The instruction is decoded to determine what action is required.
B. The processor reads an instruction from memory (cache, main memory).
C. The execution of an instruction may require performing some arithmetic or logical operation on data.
D. The results of an execution may require writing data to memory or an I/O module.
What is a drawback of Instruction Pipelining?
A. It increases the instruction throughput
B. It allows more CPU throughput than a multicycle computer at a given ck rate
C. It may increase latency due to the added overhead of the pipelining process itself
D. It decreases the complexity of the computer system
What is a primary disadvantage of CISC (Complex Instruction Set Computer) architectures?
A. Increased implementation complexity
B. Limited instruction set
C. Slower execution due to complex instructions
D. Higher energy consumption
What is the primary method used to cope with storage conflicts in registers?
A. Increasing the size of the instruction set
B. Register renaming
C. Using shared memory
D. Using technique of out-of-order issue with out-of-order completion
What is a scalar instruction?
A. An instruction in which all operands must be single values.
B. An instruction in which all operands must be groups such as arrays.
C. An instruction in which all operands can be single values or groups
D. An instruction in which has no operand.
Which computing model is characterized by a large number of processors working on different parts of a problem simultaneously?
A. Single instruction, single data (SISD)
B. Single instruction, multiple data (SIMD)
C. Multiple instruction, multiple data (MIMD)
D. Multiple instruction, single data (MISD)
Which of the following types of processors typically offer better performance for parallel processing?
A. Single-core processors
B. Multi-core processors
C. Microelectronics
D. Digital signal processors (DSPs)
Follow the Amdahl's law for multiprocessors, if only 20% of the code is inherently serial (f = 0.8), running the program on a multicore system with 8 processors, a performance gain (speedup factor) would be
A. 333%
B. 303%
C. 313%
D. 323%
Choose an INCORRECT trend in contemporary processor designs.
A. The number of processes accepted is infinitive.
B. The number of integrated transistors is getting increasing and more larger
C. Higher clock frequency is applied
D. More cores are integrated in one chip.
In modern processors, why is cache memory typically organized into multiple levels, such as L1, L2, and L3 caches?
A. To balance the trade-off between speed and size by having different cache levels.
B. To conserve chip area by reducing the cache size and increasing the memory size
C. To provide redundancy in case of cache failures
D. To improve cache coherence in multi-processor systems
