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WorksheetsDigital Electronics - Modue 3 & 4
Total questions: 50
Worksheet time: 26mins
Name
Class
Date
1.
Which flip-flop stores 1-bit of data?
a)
D flip-flop
b)
T flip-flop
c)
RS flip-flop
d)
JK flip-flop
2.
Types of flip-flops include which of the following?
a)
RS FF
b)
D FF
c)
T FF
d)
All of the above
3.
D flip-flop is also known as?
a)
Data latch
b)
Toggle FF
c)
Set-only FF
d)
Async FF
4.
A ripple counter is also called?
a)
Asynchronous counter
b)
Synchronous counter
c)
Gray counter
d)
Ring counter
5.
How many states does a 2-bit counter have?
a)
2
b)
4
c)
8
d)
16
6.
Which shift register shifts data in one direction only?
a)
SISO
b)
SIPO
c)
PISO
d)
Universal Register
7.
A ring counter is a type of?
a)
Circular shift register
b)
Up counter
c)
Gray counter
d)
Johnson counter
8.
Seven-segment display is used to show?
a)
Numbers
b)
Letters
c)
Symbols
d)
Only 0–3
9.
Which FF removes invalid states of RS FF?
a)
JK flip-flop
b)
D flip-flop
c)
T flip-flop
d)
SR latch
10.
Max count of 4-bit binary counter is?
a)
7
b)
8
c)
15
d)
16
11.
JK FF toggles when J=K=?
a)
0
b)
1
c)
X
d)
No change
12.
Conversion of JK to D uses?
a)
D = J ⊕ K
b)
D = JK
c)
D = J + K'
d)
D = J'K
13.
3-bit asynchronous counter uses how many FFs?
a)
1
b)
2
c)
3
d)
4
14.
Universal shift register supports?
a)
Shift left & right
b)
Parallel load
c)
Serial in/out
d)
All operations
15.
Sequence of 4-bit ring counter?
a)
1000→0100→0010→0001
b)
0001→0011→0111→1111
c)
1010→0101→0010→0001
d)
0000→1111→0000
16.
Johnson counter states for n FFs?
a)
n
b)
2n
c)
2ⁿ
d)
2ⁿ⁺¹
17.
Which register outputs serial data?
a)
SISO
b)
SIPO
c)
PIPO
d)
Universal
18.
After 0111 in 4-bit up counter comes?
a)
1000
b)
110
c)
1111
19.
Feedback used in LFSR is?
a)
AND
b)
OR
c)
XOR
d)
NAND
20.
How many LEDs in seven-segment?
a)
5
b)
6
c)
7
d)
8
21.
4-bit synchronous up counter requires?
a)
4 JK FFs + common clock
b)
4 D FFs + ripple clock
c)
4 RS FFs
d)
4 T FFs only
22.
4-bit Johnson counter length is?
a)
4 states
b)
8 states
c)
16 states
d)
32 states
23.
Which FF best for synchronous counters?
a)
D flip-flop
b)
JK flip-flop
c)
T flip-flop
d)
RS flip-flop
24.
Maximal LFSR polynomial for 4-bit?
a)
x⁴ + x + 1
b)
x³ + 1
c)
x² + x + 1
d)
x⁴ + x³ + 1
25.
Propagation delay increases in async counters because?
a)
FFs trigger sequentially
b)
Parallel operation
c)
No clock used
d)
Extra XOR gates
26.
State representation in sequential circuits is done using?
a)
State diagram
b)
State table
c)
Transition table
d)
All of the above
27.
State reduction helps in?
a)
Reducing FFs
b)
Reducing hardware
c)
Reducing complexity
d)
All of the above
28.
Two states are equivalent if?
a)
Same outputs
b)
Same next states
c)
Same outputs & next states
d)
Different outputs
29.
Merger graph is used for?
a)
State minimization
b)
State assignment
c)
Timing analysis
d)
Fault detection
30.
State assignment maps states to?
a)
Binary values
b)
Input patterns
c)
Output functions
d)
Timing signals
31.
Lockout condition occurs when?
a)
Illegal state reached
b)
State not reachable
c)
Input stuck at 1
d)
Output incorrect
32.
Moore model outputs depend on?
a)
Present state
b)
Inputs only
c)
Next state
d)
Clock only
33.
Mealy model outputs depend on?
a)
Present state
b)
Inputs
c)
State + Inputs
d)
Output FFs
34.
Mealy machines are usually?
a)
Faster
b)
Slower
c)
Noisy
d)
Asynchronous
35.
Moore machines are usually?
a)
More stable
b)
Less stable
c)
Faster
d)
Not used
36.
Pulse mode circuits operate on?
a)
Clock pulses
b)
Level signals
c)
DC inputs
d)
Analog pulses
37.
Pulse mode design must ensure?
a)
No races
b)
No hazards
c)
No glitches
d)
All of the above
38.
State sequence detector detects?
a)
Given state pattern
b)
Faults
c)
Hazards
d)
Jitter events
39.
Real-time fault detection identifies?
a)
Stuck-at faults
b)
Delay faults
c)
Transient faults
d)
All of the above
40.
Pulse circuits require?
a)
One-hot coding
b)
Race-free coding
c)
Hazard-free logic
d)
Synchronous flip-flops
41.
Clock jitter refers to?
a)
Variation in clock period
b)
Clock stuck at 1
c)
Clock failure
d)
Phase reversal
42.
Races occur when?
a)
State changes depend on path delays
b)
Inputs change slowly
c)
Outputs change early
d)
Clock is slowed
43.
A cycle in state diagram means?
a)
Repetitive states
b)
State reduction possible
c)
Race condition
d)
Faulty design
44.
Hazards occur due to?
a)
Unequal propagation delays
b)
Clock jitter
c)
Wrong coding
d)
Slow FFs
45.
Static-1 hazard means?
a)
Output glitches to 0
b)
Output glitches to 1
c)
Output stuck at 1
d)
Input unstable
46.
Essential hazards occur due to?
a)
Unequal feedback delays
b)
Low clock jitter
c)
Slow FFs
d)
High fan-out
47.
Hazard-free realization uses?
a)
Consensus terms
b)
Fewer gates
c)
Extra FFs
d)
Complimentary outputs
48.
AND-OR hazard elimination is done using?
a)
Consensus theorem
b)
DeMorgan’s law
c)
Absorption law
d)
Involution law
49.
In eliminating hazards, we add?
a)
Redundant terms
b)
Extra FFs
c)
Extra clocks
d)
Extra inputs
50.
Primary goal of state reduction is?
a)
Simpler circuit
b)
Costly circuit
c)
More FFs
d)
More hazards
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