When the input is at logic 0

When the input is at logic 1

During the transition when both PMOS and NMOS are partially ON

Only during the discharging of the load capacitor

It increases exponentially as $$V_t$$ increases

It increases exponentially as $$V_t$$ decreases

It is independent of $$V_t$$

It only exists when $$V_{gs} > V_t$$

Switching power

Short circuit power

Static/Leakage power

Dynamic power

It decreases because the current has less time to flow

It increases because both transistors stay in the saturation/linear region longer

It has no impact on power

It eliminates leakage current

The number of buffers

The distributed RC network of the long wire

The supply voltage magnitude

The clock frequency

NMOS must be 2.5x larger than PMOS

PMOS width must be increased to match the switching resistance of the NMOS

Both must be the minimum size to save area

PMOS should be removed and replaced with a resistor

$$C_L$$ decreases

$$C_L$$ increases

$$C_L$$ remains unchanged

Resistance increases proportionally

HVT (High Threshold)

SVT (Standard Threshold)

LVT (Low Threshold)

RVT (Regular Threshold)

In the capacitor itself

In the NMOS transistor

In the PMOS transistor resistance

In the clock source

Because power consumption would be too high

Because of manufacturing process variations (PVT) and uneven flop distribution

Because EDA tools cannot calculate it

Because it would require infinite buffers

Higher power consumption

Total loss of functional synchronization

Decreased latency

Increased leakage

Logic Depth

Pulse Width/Signal Shape

Supply Voltage

Transistor Count

Increased area

Sensitivity to on-chip variation (OCV) and temperature fluctuations

Reduced static power

Faster setup time

High threshold voltage

Signal Integrity/Crosstalk from an aggressor net

Adding too many decoupling capacitors

Using HVT cells

The difference between two clock arrivals

The time taken for a signal to transition between 10-90% or 20-80% of Vdd

The total delay from source to sink

The frequency of the clock

It increases leakage

It reduces the effective window for data transfer since both edges are used

It increases the number of metal layers

It has no effect on DDR

To reduce the number of transistors

To minimize the impact of external noise and variations on the clock path

To increase the clock period

To simplify the GDSII file

Global Latency

Local Skew

Slew Rate

Duty Cycle distortion

The flop may fail to toggle or capture data

The chip will run faster

Leakage power will decrease

Area will be optimized

The delay decreases (Negative Crosstalk)

The delay increases (Positive Crosstalk)

A glitch is always created

The net becomes an aggressor

To reduce the resistance of the clock wire

To provide a constant capacitance to ground and block coupling from neighbors

To increase the switching speed of the clock

To save area in the routing layers

A physical barrier of oxide

VSS or VDD lines placed between signal nets to prevent crosstalk

A high-resistance wire

A layer of high-density metal

It reduces the coupling capacitance directly

It "breaks" the victim net into shorter segments, increasing its drive strength

It increases the voltage of the signal

It eliminates the aggressor net

Spacing has no effect

Increasing spacing reduces $$C_M$$ and thus crosstalk

Decreasing spacing reduces crosstalk

Doubling the spacing quadruples the crosstalk

The stable period of a data signal

The active edge of a clock signal

The power-down mode

The fabrication process

The root (lowest resistance)

Long global routes between levels of the H-Tree

The local routes to the flops

The feedback path

Audible noise from the chip

Logic failures caused by crosstalk-induced glitches

Thermal noise in resistors

Power supply ripple

Increase the skew

Act as a local energy reservoir to prevent Vdd droop during switching

Block DC current

Reduce the chip area

All wires are the same width

The path length from the root to every leaf is identical

It uses the minimum amount of metal

It only uses vertical routing

To increase the total capacitance

To isolate the upstream RC from the downstream RC and maintain signal transition

To reduce the number of metal layers

To increase the clock frequency

4

8

16

32

Partitioning the chip into smaller, symmetrical sectors with local clock trees

Using only one giant buffer at the root

Removing all flops to simplify routing

Routing the clock manually for every flop

Because of the "Uneven Spread" caused by logic density and macro placement

Because engineers prefer random placement

Because H-Trees are prohibited by EDA tools

To increase the chip's power consumption

The tree becomes perfectly balanced

Some branches will have longer "detour" routing, increasing skew

The power consumption becomes zero

The clock frequency must be halved

It adds "dummy" loads or delay buffers to the 10-flop branch

It ignores the difference

It reduces the voltage to the 100-flop branch

It removes 90 flops from the second branch

The level containing the final sinks (flops) driven by the tree

The level containing the root buffer

Mid-level branching nodes

The metal layer used for clock routing

To make the GDSII file look symmetrical

To ensure the wire length to each sector's center is the same

To reduce the number of transistors in each sector

To simplify the power grid

Different for every branch

The same for all paths from root to leaf

Zero

Only dependent on the buffer size

It has fewer stages (one instead of two), potentially reducing latency and power

It is larger in size

It cannot be used for clocks

It has higher resistance

The number of levels must be odd

The number of levels must be even to maintain the clock polarity

The number of levels doesn't matter

You cannot use an even number of levels

Equal $$T_{rise}$$ and $$T_{fall}$$

Maximum possible leakage

Minimum area regardless of performance

No PMOS transistors

Increase the width ( $$W$$ ) of the PMOS

Increase the length ( $$L$$ ) of the NMOS

Reduce the supply voltage

Use HVT for NMOS and LVT for PMOS

They use less power than regular buffers

They are larger ( $$W_{PMOS}$$ is high), which increases parasitic capacitance and switching power

They have zero leakage

They reduce the battery life of the EDA tool

Processing multiple clock trees for different chips at once

Using parallel processing to compute routing for millions of flops simultaneously

Routing one wire at a time with one processor

Increasing the number of metal layers

A single wire

A mesh of wires across the chip

A series of H-Trees

Wireless signals

H-Tree

Clock Mesh/Grid

Fishbone Tree

Daisy Chain

To change the clock frequency

To act as repeaters to combat the $$L^2$$ delay effect of long wires

To increase the voltage

To reduce the number of flops

Only the wire capacitance

The wire capacitance plus the input capacitance of the buffers at level $$N+1$$

Only the flip-flop capacitance

The power grid capacitance

To increase the clock speed

To reduce dynamic power by disabling the clock to idle modules

To fix setup violations

To reduce the area of the chip

AND gate or OR gate

XOR gate

NOT gate

Buffer

Synchronized to prevent glitches on the clock line

Always high

Always low

A high-frequency signal

A simple AND gate

A combination of a latch and an AND/OR gate

A high-speed inverter

A decoupling capacitor

As close to the sinks as possible

As close to the root of the tree as possible to save maximum power

Only in the middle levels

Inside the flip-flop

It saves too much power

It can cause massive timing violations if the "Enable" signal is slow

It increases the number of buffers

It reduces the area

Fall time

Frequency of the clock

Force of the signal

Fabrication layer

It has no impact

It can introduce additional skew because of the gating logic delay

It always reduces skew to zero

It eliminates the need for CTS

Switching power

Short circuit power

Static/Leakage power (since Vdd is still applied)

Dynamic power

Maximize the number of buffers

Minimize the total wire length and the number of switching buffers

Use only LVT cells

Increase the duty cycle to 100%

100 ps

0 ps

Infinite

Dependent on the library

It improves

It degrades because of actual skew and latency

It remains exactly the same

It becomes zero

Required Arrival Time and Actual Data Arrival Time

Clock Period and Latency

Rise Time and Fall Time

Vdd and Vss

The path from the clock source to the Capture Flop

The path from the clock source, through the Launch Flop, to the input of the Capture Flop

The path from the Data input to the Data output

The reset signal path

The delay of the combinational logic

The clock path delay from the source to the clock pin of the Capture Flop

The delay of the Launch Flop

The hold time of the library

Increase the delay of the launch path

Decrease the delay of the launch path or increase the delay of the capture path (Useful Skew)

Increase the clock frequency

Increase the data path delay

It consumes too much area

It might create a Hold violation in the same stage or a Setup violation in the next stage

It reduces the voltage

It changes the logic function

The same edge (or the immediate next edge depending on the check)

The previous edge

Ten edges later

Only at power-on

Data arrives too late

Data arrives too early and changes before it is safely captured

The clock frequency is too low

The skew is zero

Variations in the clock source and environmental noise

The number of metal layers

The size of the chip

The cost of the fabrication

The capture clock arrives after the launch clock

The capture clock arrives before the launch clock

The skew is zero

The latency is negative

It makes it harder to meet setup (reduces slack)

It makes it easier to meet setup (increases slack)

It has no effect

It causes the chip to melt

It makes it easier to meet hold

It makes it harder to meet hold (increases risk of violation)

It eliminates hold checks

It reduces leakage

The capture clock arrives earlier than the launch clock

The capture clock arrives later than the launch clock

The clock period is negative

The design uses only PMOS

Negative Skew

Positive Skew

Zero Skew

Infinite Skew

Setup violation

Hold violation

Both setup and hold violations

Neither setup nor hold violation

Setup Violation

Hold Violation

Power Violation

Area Violation

Remove buffers from the data path

Add buffers (delay) to the data path

Increase the clock frequency

Decrease the supply voltage

+1ns

-1ns (Violation)

9ns

0ns

+0.3ns (Met)

-0.3ns (Violation)

1.3ns

0.5ns

Trying to reach zero skew everywhere

Intentionally unbalancing the clock tree to resolve timing violations

Using only one metal layer for the clock

Removing the clock gating

Routing at 45-degree angles

Routing only in horizontal and vertical directions

Routing in a circular pattern

Wireless interconnects

It's too fast

It's difficult to manufacture and represent in the GDSII/mask format

It uses less area

It reduces capacitance

Connect two different metal layers

Increase the resistance of a wire

Act as a buffer

Store charge

Lower metal layers (M1, M2) because they are thinner

Top/Higher metal layers because they are thicker and have lower resistance

Only the polysilicon layer

Any layer chosen at random

The clock signal never switches

The clock signal switches at a very high frequency, leading to high average current density

The clock tree has no buffers

The voltage is too low

Use thinner wires

Use wider wires or multiple vias to handle the high current

Reduce the clock frequency to 1Hz

Remove the decoupling capacitors

It defines the physical boundaries and macro locations, which determines the global skew

It has no impact

It only affects the power grid

It is done after CTS

Too many people in the lab

Areas where the routing demand exceeds the available metal resources

High temperature

Slow simulation speed

It makes routing easier

It forces long "detour" routes, which significantly increases skew and latency

It reduces the number of buffers

It improves signal integrity

Write the C++ code for the tool

Represent the final physical layout for fabrication

Simulate the logic behavior

Store the user's password

It is the cost of a single clock buffer

It is the Indian government's approved investment for three semiconductor plants

It is the revenue of Monk9 Pvt Ltd

It is the price of the Udemy course

Bangalore

Dholera

Jaipur

Poland

Intel

PSMC

Samsung

TSMC

100 chips per year

50,000 wafers per month

1 million transistors per day

50 buffers per clock tree

Verify the logic before placement

Verify the timing and functionality with extracted RC parasitics from the actual routing

Estimate the cost of the chip

Choose the name of the SoC

All timing violations (Setup/Hold) are fixed

The chip has zero power consumption

The chip is made of gold

There are no buffers in the design