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WorksheetsDE Quiz 2
Total questions: 118
Worksheet time: 2hrs 58mins
Name
Class
Date
1.
Binary coded decimal is a combination of __________ bits.
a)
two
b)
three
c)
four
d)
five
2.
What is alternate name for 8421 Binary Code?
a)
ASCII Code
b)
BCD Code
c)
EBCDIC Code
d)
GRAY Code
3.
Which of the following is an invalid BCD code?
a)
(0110)2
b)
(0011)2
c)
(1001)2
d)
(1101)2
4.
Represent decimal number (10) in its equivalent BCD form.
a)
(1010)2
b)
(0001 0000)2
c)
(1010 0000)2
d)
(0011 1010)2
5.
Identify the type of a binary code in which EACH successive code differs from its preceding (previous) code by a SINGLE BIT ONLY.
a)
BCD Code
b)
GRAY Code
c)
EBCDIC Code
d)
ASCII Code
6.
Which of the following binary code/s is/are Non-Weighted Binary Code/s?
a)
BCD Code
b)
GRAY Code
c)
EBCDIC Code
d)
Both b & c
7.
Find out equivalent Excess-3 Code for the given Decimal number (6).
a)
(0110)2
b)
(0011)2
c)
(1001)2
d)
(1101)2
8.
How many individual bits are used by an ASCII code to represent any given character?
a)
3
b)
4
c)
7
d)
8
9.
How many individual bits are used by an EBCDIC code to represent any given character?
a)
3
b)
4
c)
7
d)
8
10.
Which of the following circuit is used to generate Parity Bit?
a)
Error Detector Circuit
b)
Parity Generator Circuit
c)
Error Correction Circuit
d)
Parity Checker Circuit
11.
Which of the following circuit is used to check Parity Bit generated is correct or not?
a)
Error Detector Circuit
b)
Parity Generator Circuit
c)
Error Correction Circuit
d)
Parity Checker Circuit
12.
A given digital binary number has even parity ______________.
a)
if it has even no. of 1s
b)
if it has even no. of 0s
c)
if it has odd no. of 1s
d)
if it has odd no. of 0s
13.
When using even parity, where is the parity bit placed?
a)
Before the MSB
b)
After the LSB
c)
In the Parity Word
d)
After the Odd Parity Bit
14.
Convert the Gray code 1011 to binary.
a)
1011
b)
1010
c)
1001
d)
1101
15.
Which of the following parameter is used to represent the symbol of logic gate?
a)
Boolean Expression
b)
Logic Symbol
c)
Timing Diagram
d)
Truth Table
16.
Which of the following parameter will give the possible input-output combinations of a logic gate?
a)
Boolean Expression
b)
Logic Symbol
c)
Timing Diagram
d)
Truth Table
17.
Which of the following parameter is used to represent equation or expression of logic gate?
a)
Boolean Expression
b)
Logic Symbol
c)
Timing Diagram
d)
Truth Table
18.
Which of the following parameter is used to represent graphical representation of input and output signals of logic gate wrt time?
a)
Boolean Expression
b)
Logic Symbol
c)
Timing Diagram
d)
Truth Table
19.
When used with an Logic Gate IC, what does the term "QUAD" indicate?
a)
IC with 2 logic gates
b)
IC with 4 logic gates
c)
IC with 6 logic gates
d)
IC with 8 logic gates
20.
Which of the following logic gate is NOT a type of basic gate?
a)
AND Gate
b)
OR Gate
c)
NOT Gate
d)
NOR Gate
21.
Which of the following logic gate is an Universal gate?
a)
AND Gate
b)
OR Gate
c)
NAND Gate
d)
EX-OR Gate
22.
Which of the following type of logic gate performs basic logic functions?
a)
Basic Gates
b)
Exclusive Gates
c)
Universal Gates
d)
None of the above
23.
Which of the following logic gate performs complementation?
a)
AND Gate
b)
OR Gate
c)
NOT Gate
d)
NAND Gate
24.
Which of the following logic gate performs logical addition?
a)
AND Gate
b)
OR Gate
c)
NOT Gate
d)
NAND Gate
25.
Which of the following logic gate performs logical multiplication?
a)
AND Gate
b)
OR Gate
c)
NOT Gate
d)
NAND Gate
26.
Identify the logic gate, where the normally open switches are connected in parallel as inputs and Lamp as output?
a)
AND Gate
b)
OR Gate
c)
NOT Gate
d)
NAND Gate
27.
Identify the logic gate, where the normally open switches are connected in series as inputs and Lamp as output?
a)
AND Gate
b)
OR Gate
c)
NOT Gate
d)
NAND Gate
28.
If either of inputs A or B of a logic gate is true, then output Q is true. Identify the logic gate.
a)
AND Gate
b)
OR Gate
c)
NOT Gate
d)
NAND Gate
29.
If both of inputs A or B of a logic gate is true, then output Q is true. Identify the logic gate.
a)
AND Gate
b)
OR Gate
c)
NOT Gate
d)
NAND Gate
30.
Which of the following type of logic gate performs function of any logic gate or any Boolean expression?
a)
Basic Gates
b)
Exclusive Gates
c)
Universal Gates
d)
None of the above
31.
Which of the following logic gate performs Complement of OR Operation?
a)
AND Gate
b)
NOR Gate
c)
NOT Gate
d)
NAND Gate
32.
Which of the following logic gate performs Complement of AND Operation?
a)
AND Gate
b)
NOR Gate
c)
NOT Gate
d)
NAND Gate
33.
If either of inputs A or B are LOW, then output Q is HIGH. Identify the logic gate.
a)
AND Gate
b)
OR Gate
c)
NOT Gate
d)
NAND Gate
34.
If and ONLY if both the inputs A and B are LOW, then output Q is HIGH. Identify the logic gate.
a)
NOR Gate
b)
OR Gate
c)
NOT Gate
d)
NAND Gate
35.
Which of the following type of logic gate performs special logic functions?
a)
Basic Gates
b)
Exclusive Gates
c)
Universal Gates
d)
None of the above
36.
If both the inputs A and B are at DIFFERENT voltage levels, then ouptut Q is true”. Identify the logic gate.
a)
OR Gate
b)
EX-OR Gate
c)
NOR Gate
d)
NAND Gate
37.
If both the inputs A and B are at SAME voltage levels, then ouptut Q is true”. Identify the logic gate.
a)
OR Gate
b)
EX-OR Gate
c)
NOR Gate
d)
EX-NOR Gate
38.
Identify the logic gate which is suitable for bit comparison.
a)
Two input OR Gate
b)
Two input EX-OR Gate
c)
Two input NOR Gate
d)
Two input EX-NOR Gate
39.
An EX-OR gate output is HIGH if _______________________.
a)
it has ODD no. of 1s in the inputs
b)
it has EVEN no. of 1s in the inputs
c)
it has ALL inputs are 0s
d)
it has ALL inputs are 1s
40.
How many NAND gate/s is/are required to build the INVERTER gate?
a)
1
b)
2
c)
3
d)
4
41.
How many NAND gates are required to build the AND gate?
a)
1
b)
2
c)
3
d)
4
42.
How many NAND gates are required to build the OR gate?
a)
1
b)
2
c)
3
d)
4
43.
How many NAND gates are required to build the NOR gate?
a)
1
b)
2
c)
3
d)
4
44.
How many NAND gates are required to build the EX-OR gate?
a)
1
b)
2
c)
3
d)
4
45.
How many NOR gate/s is/are required to build the INVERTER gate?
a)
1
b)
2
c)
3
d)
4
46.
How many NOR gates are required to build the OR gate?
a)
1
b)
2
c)
3
d)
4
47.
How many NOR gates are required to build the AND gate?
a)
1
b)
2
c)
3
d)
4
48.
How many NOR gates are required to build the NAND gate?
a)
1
b)
2
c)
3
d)
4
49.
How many NOR gates are required to build the EX-OR gate?
a)
2
b)
3
c)
4
d)
5
50.
The rise time (tr) is the time it takes for a pulse to rise from its ________ point up to its ________ point.
a)
10%, 90%
b)
90%, 10%
c)
20%, 80%
d)
80%, 20%
51.
The fall time (tf) is the length of time it takes to fall from the ________ to the ________ point.
a)
10%, 90%
b)
90%, 10%
c)
20%, 80%
d)
80%, 20%
52.
A positive-going pulse is applied to an inverter. The time interval from the leading edge of the input to the leading edge of the output is 7 ns. This parameter is ___________.
a)
speed-power product
b)
propagation delay, tPHL
c)
propagation delay, tPLH
d)
pulse width
53.
Identify the performance paremater of a logic gate which defines the time needed for an output to change from the result of an input change.
a)
speed-power product
b)
propagation delay
c)
power dissipation
d)
noise margin
54.
When will the output of logic gate experience a Worst Propogation Delay?
a)
Logic gate has MIN DELAY
b)
Logic gate has AVE DELAY
c)
Logic gate has MAX DELAY
d)
Logic gate has NO DELAY
55.
When will the output of logic gate experience a FASTEST CHANGE, when an input change is there?
a)
Logic gate has MIN DELAY
b)
Logic gate has AVE DELAY
c)
Logic gate has MAX DELAY
d)
None of the above
56.
When will the output of logic gate experience a Typical Propogation Delay?
a)
Logic gate has MIN DELAY
b)
Logic gate has AVE DELAY
c)
Logic gate has MAX DELAY
d)
Logic gate has NO DELAY
57.
Logic Gate A has tPLH = tPHL = 6 ns. Logic Gate B has tPLH = tPHL = 10 ns. Which logic gate can be operated at a higher frequency?
a)
Logic Gate A
b)
Logic Gate B
c)
Neither Logic Gate A nor Logic Gate B
d)
Either Logic GateA or Logic Gate B
58.
Identify the performance paremater of a logic gate which defines the no. of inputs to the logic gate.
a)
Rise Time
b)
Fan In
c)
Fall Time
d)
Fan Out
59.
Identify the performance paremater of a logic gate which defines the no. of inputs which can be driven by a SINGLE Logic Gate Ouput.
a)
Rise Time
b)
Fan In
c)
Fall Time
d)
Fan Out
60.
Identify the performance paremater of a logic gate which defines the PRODUCT of dc supply voltage (Vcc) & the average supply current (Iave).
a)
Rise Time
b)
Fall Time
c)
Propogation Delay
d)
Power Dissipation
61.
If a logic gate operates on a dc supply voltage of +5 V and draws an average current of 4 mA, what is its power dissipation?
a)
15 mA
b)
20 mA
c)
25 mA
d)
30 mA
62.
Identify the performance paremater of a logic gate which defines the product of propogation delay & average power dissipation.
a)
Rise Time
b)
Fall Time
c)
Speed Power Product
d)
Noise Margin
63.
Identify the performance paremater of a logic gate which is also termed as Figure of Merit.
a)
Rise Time
b)
Fall Time
c)
Speed Power Product
d)
Noise Margin
64.
Identify the unit of Speed-Power Product (SPP).
a)
seconds
b)
Watts
c)
Hertz
d)
Joules
65.
If the propagation delay of a gate is 15 ns and its Speed Power Product (SPP) is 150 pJ, what is its average power dissipation?
a)
1 mW
b)
10 mW
c)
100 mW
d)
10 W
66.
A certain gate has a propagation delay time of 6 ns and a power dissipation of 3 mW. Determine the speed-power product?
a)
9 pJ
b)
3 pJ
c)
18 pJ
d)
2 pJ
67.
Identify the performance paremater of a logic gate which defines the amount of noise that the logic gate can withstand while still functioning properly.
a)
Power Dissipation
b)
Propagation Delay Time
c)
Noise Margin
d)
Figure of Merit
68.
Identify the term of Boolean Algebra which is used to represent an action, a condition, or data.
a)
Complement
b)
Literal
c)
Variable
d)
None of the above
69.
A variable is a symbol in Boolean algebra used to represent
a)
Data
b)
A Condition
c)
An Action
d)
All of the Above
70.
Identify the term of Boolean Algebra which will give the inverse of variable.
a)
Complement
b)
Literal
c)
Variable
d)
None of the above
71.
Identify the term of Boolean Algebra which will represent a variable or the complement of the variable.
a)
Complement
b)
Literal
c)
Variable
d)
None of the above
72.
The Boolean expression A + B + C is
a)
complement
b)
literal term
c)
product term
d)
sum term
73.
The Boolean expression A . B . C is
a)
complement
b)
literal term
c)
product term
d)
sum term
74.
Determine the values of A, B, and C that make the sum term A' + B' + C = 0.
a)
A = 0 ; B = 0 ; C = 0
b)
A = 1 ; B = 1 ; C = 0
c)
A = 1 ; B = 0 ; C = 1
d)
A = 1 ; B = 1 ; C = 1
75.
Determine the values of A, B, and C that make the product term AB'C equal to 1.
a)
A = 0 ; B = 0 ; C = 0
b)
A = 1 ; B = 1 ; C = 0
c)
A = 1 ; B = 0 ; C = 1
d)
A = 1 ; B = 1 ; C = 1
76.
Identify the boolean expression for associative law of addition from the following.
a)
A + B = B + A
b)
A = A + A
c)
(A + B) + C = A + (B + C )
d)
A + 0 = A
77.
Identify the boolean expression for commutative law of multiplication from the following.
a)
A . B = B . A
b)
A = A . A
c)
(A . B) . C = A . (B . C )
d)
A . 0 = 0
78.
Identify the boolean expression for distributive law.
a)
A(B + C) = AB + AC
b)
A(BC) = ABC
c)
A(A + 1) = A
d)
A + AB = A
79.
Which one of the following is not a valid rule of Boolean algebra?
a)
A + 1 = 1
b)
A = A'
c)
AA = A
d)
A + 0 = A
80.
Which of the following rules states that if one input of an AND gate is always 1, the output is equal to the other input?
a)
A + 1 = 1
b)
A + A = A
c)
A . A = A
d)
A . 1 = A
81.
According to DeMorgan’s theorems, the complement of a product of variables is equal to
a)
the complement of the sum
b)
the sum of the complements
c)
the product of the complements
d)
None of the above
82.
An example of a canonical SOP expression is
a)
A'B + AB'C + ABD'
b)
AB'C + AC'D
c)
A'B + AB' + AB
d)
AB'CD' + A'B + A'
83.
An example of a standard SOP expression is
a)
AB+C
b)
ABC + A'BC
c)
A'B'CD + AB'C'D'
d)
(A+B)(A'+B')
84.
The Boolean expression X = (A + B)(C + D) represents
a)
two ORs ANDed together
b)
two ANDs ORed together
c)
a 4-input AND gate
d)
a 4-input OR gate
85.
A 2-variable Karnaugh map has
a)
4 cells
b)
8 cells
c)
16 cells
d)
32 cells
86.
A 2-variable Karnaugh map has
a)
4 singles, 4 pairs, 1 quad, 0 Octets
b)
2 singles, 2 pairs, 1 quad, 0 Octets
c)
2 singles, 4 pairs, 1 quad, 0 Octets
d)
4 singles, 2 pairs, 1 quad, 0 Octets
87.
A 3-variable Karnaugh map has
a)
4 cells
b)
8 cells
c)
16 cells
d)
32 cells
88.
A 3-variable Karnaugh map has
a)
8 singles, 8 pairs, 2 quad, 0 Octets
b)
8 singles, 4 pairs, 2 quad, 0 Octets
c)
8 singles, 8 pairs, 4 quad, 1 Octets
d)
8 singles, 12 pairs, 6 quad, 1 Octets
89.
A 4-variable Karnaugh map has
a)
4 cells
b)
8 cells
c)
16 cells
d)
32 cells
90.
A 4-variable Karnaugh map has
a)
16 singles, 12 pairs, 16 quad, 2 Octets
b)
16 singles, 16 pairs, 18 quad, 4 Octets
c)
16 singles, 32 pairs, 24 quad, 8 Octets
d)
16 singles, 12 pairs, 6 quad, 2 Octets
91.
In a 4-variable SoP Karnaugh map, a 2-variable product term is obtained by
a)
a QUAD of adjacent 1s
b)
an OCTET of adjacent 1s
c)
a PAIR of adjacent 1s
d)
a QUAD of adjacent 0s
92.
In a 4-variable SoP Karnaugh map, a 3-variable product term is obtained by
a)
a QUAD of adjacent 1s
b)
an OCTET of adjacent 1s
c)
a PAIR of adjacent 1s
d)
a QUAD of adjacent 0s
93.
In a 4-variable SoP Karnaugh map, a SINGLE-variable is obtained by
a)
a QUAD of adjacent 1s
b)
an OCTET of adjacent 1s
c)
a PAIR of adjacent 1s
d)
a QUAD of adjacent 0s
94.
In a 4-variable SoP Karnaugh map, a 4-variable product term is obtained by
a)
a QUAD of adjacent 1s
b)
an OCTET of adjacent 1s
c)
a PAIR of adjacent 1s
d)
a SINGLE 1 with NO adjacent 1s
95.
In a 4-variable SoP Karnaugh map, a PAIR is formed by grouping adjacent
a)
two 1s
b)
four 1s
c)
eight 1s
d)
sixteen 1s
96.
In a 4-variable SoP Karnaugh map, a QUAD is formed by grouping adjacent
a)
two 1s
b)
four 1s
c)
eight 1s
d)
sixteen 1s
97.
In a 4-variable SoP Karnaugh map, an OCTET is formed by grouping adjacent
a)
two 1s
b)
four 1s
c)
eight 1s
d)
sixteen 1s
98.
In a 4-variable PoS Karnaugh map, a PAIR is formed by grouping adjacent
a)
two 1s
b)
four 1s
c)
two 0s
d)
four 0s
99.
In a 4-variable PoS Karnaugh map, a QUAD is formed by grouping adjacent
a)
two 1s
b)
four 1s
c)
two 0s
d)
four 0s
100.
In a 4-variable PoS Karnaugh map, an OCTET is formed by grouping adjacent
a)
four 1s
b)
eight 1s
c)
four 0s
d)
eight 0s
101.
How many inputs & outputs does Full Adder Circuit have?
a)
2 inputs ; 3 outputs
b)
2 inputs ; 2 outputs
c)
3 inputs ; 2 outputs
d)
3 inputs ; 3 outputs
102.
How many inputs & outputs does Half Adder Circuit have?
a)
2 inputs ; 3 outputs
b)
2 inputs ; 2 outputs
c)
3 inputs ; 2 outputs
d)
3 inputs ; 3 outputs
103.
A full adder circuit can be realized using __________.
a)
One Half Adder & One OR Gate
b)
Two Half Adders & One OR Gate
c)
Two Half Adders & Two OR Gates
d)
One Half Adder & Two OR Gates
104.
A half adder circuit can be realized using __________.
a)
One EX-OR Gate & One AND Gate
b)
One EX-OR Gate & One OR Gate
c)
One EX-NOR Gate & One AND Gate
d)
One EX-NOR Gate & One OR Gate
105.
A 3-bit parallel adder can add
a)
three 2-bit binary numbers
b)
two 3-bit binary numbers
c)
three bits at a time
d)
three bits in sequence
106.
Which gate is best used as a basic comparator?
a)
NOR
b)
OR
c)
Exclusive-OR
d)
AND
107.
If a 74HC85 magnitude comparator has A = 1000 and B = 1010, the outputs are
a)
A > B = 0; A < B = 0; A = B = 0
b)
A > B = 0; A < B = 0; A = B = 1
c)
A > B = 0; A < B = 1; A = B = 0
d)
A > B = 1; A < B = 0; A = B = 0
108.
If an octal-to-binary priority encoder has its 0, 2, 5, and 6 inputs at the active level, the active-HIGH binary output is
a)
(110)2
b)
(010)2
c)
(101)2
d)
(000)2
109.
If a 3-to-8 line decoder with active-LOW outputs exhibits a LOW on the decimal 6 output, what are the status of inputs?
a)
C = 1; B = 0; A = 1
b)
C = 1; B = 0; A = 0
c)
C = 1; B = 1; A = 0
d)
C = 0; B = 1; A = 0
110.
A decoder can be used as a demultiplexer by ________.
a)
connecting all enable pins to LOW LOGIC
b)
connecting all data pins to LOW LOGIC
c)
connecting all data pins to HIGH LOGIC
d)
using the input lines for data selection and an enable line for data input
111.
Which of the following combinational circuit is also termed as Data Selector?
a)
Decoder
b)
Demultiplexer
c)
Multiplexer
d)
Encoder
112.
How many data select lines are required for selecting eight data inputs?
a)
two
b)
three
c)
four
d)
five
113.
In an 8-to-1 multiplexer, it consists of
a)
1 data input
8 outputs and
3 inputs
b)
1 data input
1 data output and
1 selection input
c)
8 data inputs
3 data outputs and
3 selection inputs
d)
8 data inputs
1 data output and
3 selection inputs
114.
Which of the following combinational circuit is also termed as Data Distributor?
a)
Decoder
b)
Demultiplexer
c)
Multiplexer
d)
Encoder
115.
Identify the combinational circuit based IC which has one data input, two data select inputs, one enable input & four data output lines.
a)
Encoder
b)
Decoder
c)
Multiplexer
d)
demultiplexer
116.
Which of the following bit is used to detect the error in the binary data?
a)
Carry Bit
b)
Parity Bit
c)
Auxiliary Carry Bit
d)
Overflow Bit
117.
Which of the following logic gate is used to construct the Parity Generator & Checker combinational circuits?
a)
EX-OR logic gate
b)
OR logic gate
c)
NAND logic gate
d)
NOR logic gate
118.
Which of the following codes exhibit even parity?
a)
(10011000)2
b)
(01111000)2
c)
(11111110)2
d)
(11010101)2
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