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WorksheetsECET TEST - 3 CORE
Total questions: 150
Worksheet time: 1hrs 15mins
Which of the following is a universal gate?
AND
XOR
OR
NAND
Which of the following is NOT a combinational circuit?
Flip-Flop
Multiplexer
Decoder
Adder
A demultiplexer is a device that ________.
encodes multiple inputs into one output
decodes binary numbers to decimal
stores binary information in registers
routes a single input to multiple outputs
Convert the binary number 110011 to its decimal equivalent.
49
51
53
55
Which component pairs with a multiplexer to perform opposite routing functions in digital circuits?
Adder
Encoder
Demultiplexer
Register
When converting 110011₂ to decimal, which positional weights are applied to the six bits from right to left?
1, 2, 4, 8, 16, 32
1, 3, 9, 27, 81, 243
2, 4, 8, 16, 32, 64
0, 1, 2, 3, 4, 5
In a demultiplexer, what determines which output line receives the input signal?
power supply voltage
address or select inputs
clock pulses only
feedback from outputs
Which statement best distinguishes a demultiplexer from an encoder?
Demultiplexer distributes one input to many lines
Demultiplexer increases bit-width of outputs
Encoder converts decimal values to binary
Encoder routes one input to many outputs
Given the bit pattern 110011₂, which bits contribute to the value 32 + 16?
the two least significant bits
no bits contribute those weights
the two most significant bits
the middle two bits
If a demultiplexer has 3 select lines, how many possible output lines can it address?
16 lines
8 lines
6 lines
4 lines
Which error most likely leads to an incorrect decimal result when converting 110011₂?
ignoring the least significant bit
doubling the sum after conversion
using base ten positional weights
adding weights for zero bits
A system needs to send one data stream to any of eight destinations. Which device is the most suitable?
Adder with carry-in control
Demultiplexer with three selects
Encoder with three outputs
Register with parallel load
The number of select lines required for an 8-to-1 multiplexer is?
4
3
2
5
A sequential logic circuit that toggles its output state on each clock pulse is a:
T flip-flop
D flip-flop
SR flip-flop
JK flip-flop
Convert the decimal number 108 into its octal equivalent.
152
160
124
154
For an 8-to-1 multiplexer, the relationship between inputs and select lines is best described as:
Inputs equal select lines minus one
Inputs equal 2selectlines
Inputs equal select lines
Select lines equal 2inputs
Which flip-flop is specifically designed to toggle when its input is high on the clock edge?
T flip-flop with T=0
JK flip-flop with J=K=1
D flip-flop with D=1
SR flip-flop with S=R=1
Given a decimal number N, which method correctly converts N to octal?
Multiply by eight repeatedly
Subtract powers of ten iteratively
Divide by eight and read remainders
Divide by two and group bits
If a multiplexer has k select lines, how many input lines can it choose from?
2k
k inputs
k2 inputs
2k inputs
Which statement about SR and D flip-flops is accurate regarding toggling behavior?
SR toggles when S=R=1
D toggles only on rising edges
SR always holds previous state
D outputs follow input, not toggle
What is the octal representation of the binary number 1101100?
160
152
124
154
A JK flip-flop behaves like which flip-flop when J and K are tied together and driven as a single input?
Master–slave flip-flop
SR flip-flop
D flip-flop
T flip-flop
What is the simplified form of the Boolean expression (A + B)(A + C)?
A + B + C
A + BC
AB + C
AC + BC
Which statement best describes the primary purpose of a Software Requirements Specification (SRS) document?
To plan the project schedule
To describe the functional and non-functional requirements
To outline the software design
To define the coding standards
Using Boolean algebra, which identity justifies reducing (A + B)(A + C) to A + BC?
Idempotent and absorption laws
Commutative and distributive laws
Associative and consensus theorem
De Morgan’s and complement laws
In an SRS, which content is typically included to ensure clarity for stakeholders?
Post-release marketing strategies
Functional requirements with constraints
Detailed UI color palette tables
Algorithm pseudocode for modules
If A = 1, B = 0, and C = 1, what is the value of (A + B)(A + C)?
Depends on B only
Undefined
1
0
Which artifact most directly translates the SRS into implementable tasks?
Detailed design specification
High-level architecture
Test plan document
Deployment checklist
Which Boolean expression is equivalent to A + BC under consensus theorem application?
A(B + C)
(A + B + C)
AB + AC
(A + B)(A + C)
In a well-written SRS, which property best ensures requirements are testable?
Ambiguous phrasing allowed
Informal stakeholder notes
Traceability maintained
High-level vision only
Which step should you take to verify the simplification of (A + B)(A + C) = A + BC?
Apply De Morgan’s to both terms
Construct a truth table comparison
Introduce a new variable D
Factor out B from the expression
Which risk arises if an SRS omits non-functional requirements?
Too many integration tests
Performance and reliability gaps
Unclear deployment timeline
Overly strict coding rules
Which SDLC phase typically includes a feasibility study to assess constraints and viability?
Planning and analysis activities
Maintenance and support
Implementation and deployment
Testing and defect triage
In the classic waterfall model, what is the second phase following requirements?
Implementation coding tasks
Design specification creation
Maintenance and upgrades
Verification and validation
Which activity is primarily intended to find defects before release?
System testing execution
Requirements elicitation
Post‑release maintenance
High‑level architecture
During planning in SDLC, which deliverable best captures project feasibility?
Feasibility assessment report
Change management logs
Refactored code modules
Detailed test scenarios
Which sequence correctly reflects early waterfall flow?
Maintenance then design
Testing then design
Requirements then design
Implementation then design
What risk arises if design is skipped and coding starts directly?
Overly formal requirements
Architecture inconsistencies
Excess test redundancy
Delayed maintenance cycles
Which testing focus aligns with verifying design meets requirements?
Replacement of legacy tools
Optimization of compilers
Validation against user needs
Scheduling of daily standups
Which metric is most relevant during feasibility analysis?
Cost–benefit comparison
Branch coverage rate
Cyclomatic complexity
Mean time to repair
Which artifact is finalized at the end of the design phase?
System architecture specification
Defect density dashboard
End‑user training videos
Incident response playbook
Which post‑implementation activity ensures the system continues to meet needs over time?
Integration test planning
Requirements prototyping
Maintenance and enhancement
Initial feasibility screening
In Agile development, which methodology uses time-boxed sprints to deliver increments?
Waterfall follows sequential phases without sprints
Scrum organizes work into short sprints
Spiral emphasizes risk-driven iterations, not sprints
Kanban uses continuous flow without sprints
Which testing level focuses on verifying individual software components in isolation?
Integration testing checks module interactions
System testing validates end-to-end behavior
Unit testing targets single modules
Acceptance testing confirms user requirements
Which model typically delivers functional software in staged releases over time?
Waterfall delivers only at final stage
Big-bang compiles everything at once
V-model mirrors testing to development phases
Incremental model provides successive builds
A team wants continuous flow, pull-based work, and WIP limits. Which method aligns best?
Waterfall with gated milestones
Scrum with fixed-length sprints
Kanban with visual flow control
Spiral with risk analysis cycles
During integration testing, the primary goal is to identify issues in what area?
Across end-user workflows
Within a single component’s logic
Against regulatory requirements
Between interacting components
When would system testing be most appropriate in the lifecycle?
Immediately after requirements sign-off
Before any coding begins
After unit tests pass for modules
Only after deployment to production
What is a key advantage of the Incremental Model for complex projects?
Complete specification before coding
Eliminates integration challenges entirely
Early delivery of partial functionality
Single-phase verification and validation
A product owner needs frequent feedback and adaptability. Which approach best supports this?
V-model with strict mapping
Scrum with sprint reviews
Waterfall with fixed scope
Big-bang with one final release
Which activity most closely aligns with unit testing practices?
Mocking dependencies for a module
Executing full system scenarios
Evaluating performance at scale
Validating user acceptance criteria
A project faces high uncertainty and evolving risks. Which model explicitly centers on risk analysis?
Waterfall model enforces linear progression
Scrum framework focuses on time-boxed sprints
Incremental model centers on delivery cadence
Spiral model emphasizes risk assessment
Which statement best characterizes the waterfall model?
Complete product is delivered at once
Allows early detection of errors
Continuously incorporates customer feedback
Requires no planning at any stage
Which option correctly defines debugging in software development?
The process of writing code
Running a program without any issues
Identifying and fixing errors in a program
Adding new features to a program
Which type of requirement focuses on performance, reliability, and security?
Business process requirements
Functional requirements
Non-functional requirements
User interface requirements
In a waterfall approach, what is a common limitation?
High flexibility for late changes
Iterative testing with early prototypes
Limited support for customer feedback
Adaptive planning after each sprint
Which activity is part of verification rather than validation?
Evaluating usability with end users
Assessing business value in operation
Ensuring it satisfies user needs
Checking the product meets specifications
Choose the statement that best contrasts functional vs. non-functional requirements.
Functional cover reliability and scalability
Functional specify performance and security
Functional describe how well it performs
Functional describe what the system does
A team wants early error detection and frequent feedback. Which lifecycle model aligns best?
Code-and-fix approach
Agile iterative development
Traditional waterfall model
Big-bang implementation
When conducting debugging, which step is typically first?
Deploying a hotfix immediately
Optimizing performance hotspots
Refactoring unrelated modules
Reproducing the defect consistently
Which metric is most relevant to a non-functional security requirement?
Coverage of user stories delivered
Average time to compromise detected
Number of business rules implemented
Count of functional use cases
A project delivers all features only at the end of the cycle. What risk increases?
Late discovery of critical defects
Excessive customer co-creation
Too many mid-sprint requirement changes
Overuse of iterative prototypes
Which register holds the address of the next instruction to be executed?
Program Counter (PC)
Instruction Register (IR)
Stack Pointer (SP)
Memory Address Register (MAR)
Which memory holds frequently accessed data for fast retrieval?
Registers
RAM
ROM
Cache
What does the Instruction Register (IR) primarily store during execution?
Top of stack address
Next instruction address
Memory data word
Current instruction code
Which register is used to point to the top of the current stack frame?
Base Register
Program Counter
Instruction Register
Stack Pointer
Which component supplies addresses to memory during fetch operations?
Memory Address Register
Arithmetic Logic Unit
Cache Controller
Instruction Decoder
Choose the best description of a non-functional requirement in systems design.
Specific business rule to implement
Detailed algorithmic procedure
Constraint on system performance or quality
Feature that the system must perform
Business requirements primarily capture which aspect of a system?
Compiler optimization settings
Quality attributes like reliability
Hardware interface specifications
Organizational goals and outcomes
A program frequently accesses a small working set of data. Which hardware feature optimizes this pattern?
Level-1 cache memory
Large ROM segment
Extended register file
Slow external storage
If the Program Counter is accidentally modified, which immediate effect is most likely?
IR clears and halts the CPU
Cache is flushed automatically
Execution jumps to an unintended address
Stack overflows instantly
Which pairing correctly matches register to role?
PC: holds next instruction address
SP: points to base of heap
MAR: stores current instruction code
IR: holds next instruction address
The 8086 microprocessor has how many address lines?
32
20
24
16
The primary purpose of an interrupt in a microprocessor is to ________.
Organize registers
Control memory access
Execute instructions faster
Handle I/O operations efficiently
Which component is most directly responsible for permanent data storage in a typical computer system?
RAM module
Graphics card
Hard drive
CPU cache
If an 8086 system needs to address 1 MB of memory, which feature enables this capability?
On-chip DMA controller
Dedicated I/O bus
Fixed 16-bit addressing
Segmented addressing
An interrupt allows a microprocessor to respond to which kind of events most effectively?
Background computation
Asynchronous external signals
Periodic memory refresh
Sequential instruction flow
When an interrupt occurs, what typically happens to the current program execution state?
It resets the CPU
It continues uninterrupted
It is saved to a stack
It is discarded permanently
Which statement best compares address lines and data lines in a microprocessor bus?
All lines carry addresses
Control lines set timing
Data lines carry values
Address lines select locations
Why might a microprocessor use interrupt priorities?
To speed up arithmetic
To resolve simultaneous requests
To reduce clock frequency
To increase address width
Increasing the number of address lines by one generally increases the addressable space by what factor?
No significant change
Triples addressable space
Doubles addressable space
Adds one byte total
Which I/O handling technique relies on interrupts to avoid constant polling by the CPU?
Interrupt-driven I/O
Memory-mapped busy wait
Programmed I/O polling
Synchronous DMA only
Which of the following is a volatile memory?
RAM
Flash drive
ROM
Hard disk
The size of the general‑purpose registers in the 8086 microprocessor is ____.
8 bits
16 bits
32 bits
64 bits
Which CPU component coordinates and controls all activities inside the processor?
Bus interface unit
Arithmetic Logic Unit
Control Unit
Cache controller
Which storage device is non‑volatile and uses magnetic platters?
Registers
DRAM
SRAM
Hard disk
What is the primary function of the Arithmetic Logic Unit (ALU)?
Manage program flow
Execute arithmetic and logic
Handle I/O requests
Store instructions temporarily
In a typical CPU, which element temporarily holds instructions being executed?
Instruction register
Program counter
Stack pointer
Status register
Which memory type retains data without power and is used for firmware?
SRAM
ROM
Cache
DRAM
Which register tracks the address of the next instruction to fetch?
Program counter
Accumulator
Index register
Base register
Compared to ROM, RAM is primarily used for which purpose during program execution?
Temporary working data
Bootloader storage
Permanent storage
Microcode routines
Which statement best explains why RAM is called volatile?
It loses data when power is off
It stores data permanently by default
It uses magnetic storage for data
It cannot be written to by CPU
Which component performs arithmetic and logical operations in a processor?
ALU executes arithmetic and logic
Cache holds frequently used data
Control Unit manages instruction sequencing
Register File stores temporary operands
Which unit directs the flow of instructions and coordinates other components?
Control Unit orchestrates execution
ALU carries out computations
Register File buffers operands
Cache accelerates memory access
What is the primary role of the register file?
Control sequencing and scheduling
Execute arithmetic and logical operations
Store temporary operands for fast access
Hold frequently accessed memory blocks
What is the main benefit of a cache in a CPU?
Schedules threads and interrupts
Stores immediate values for instructions
Performs integer multiplication quickly
Reduces average memory access latency
Compute the binary sum: 1101 + 1010
11000
11110
10111
10011
When is the Carry Flag (CF) set in unsigned arithmetic?
No overflow but sign bit flips unexpectedly
Operation yields a zero after subtraction
An addition produces a carry out of MSB
Result becomes negative in two’s complement
Which statement correctly distinguishes CF from OF in binary addition?
CF indicates signed overflow conditions
CF is about carry out; OF about signed overflow
OF tracks borrow in subtraction only
Both CF and OF mean the same event
For 8-bit unsigned addition, what happens when 200 + 100 is computed?
Stores 44 and clears all flags
Triggers OF but not CF
Produces 300 with no flags set
Wraps modulo 256 and sets CF
Which component most directly feeds operands to the ALU during execution?
Control Unit dispatches micro-ops
Register File supplies source values
Main memory writes condition codes
Cache decodes instruction formats
What is the typical use of cache relative to registers?
Cache is larger than registers but slower
Cache holds opcodes instead of data
Cache is smaller than registers and faster
Cache executes logic while registers fetch
In two’s complement representation, which statement is true?
It is not used in modern systems
Addition needs special handling
The MSB determines the sign
The MSB is always zero
Which option is NOT an addressing mode in microprocessors?
Immediate mode
Direct mode
Indirect mode
Sequential mode
A division operation produces which characteristic outcome?
Only a sign change
Only an overflow flag
Only a remainder value
Only a carry-out bit
An arithmetic operation can result in which condition related to the most significant bit?
A borrow into the MSB
A carry out of the MSB
A zeroing of the MSB
A parity flip on the MSB
If the MSB determines the sign in two’s complement, what does an MSB of 1 indicate for a number?
The value is positive
The value is negative
The value is fractional
The value is undefined
Which addressing mode uses the operand value embedded directly within the instruction?
Immediate mode
Direct mode
Indexed mode
Indirect mode
In microprocessor addressing, which mode accesses memory via a pointer stored in a register?
Immediate mode
Direct mode
Indirect mode
Sequential mode
Which flag is most relevant when a carry is produced out of the most significant bit during addition?
Parity flag
Sign flag
Carry flag
Zero flag
During integer division, which pair of outputs is typically produced by hardware?
Quotient and remainder
Sum and difference
Product and modulus
Exponent and mantissa
Which statement best explains why two’s complement is widely used in computers?
It avoids negative numbers entirely
It requires special addition rules
It stores separate sign and magnitude
It simplifies subtraction via addition
Which ROM variant is designed to be programmed a single time and then permanently fixed?
PROM, programmed once and permanent
EEPROM, electrically erasable many times
EPROM, erasable with ultraviolet light
Flash memory, block-erasable and rewritable
Which data structure inherently follows the First In, First Out access order?
Stack, last in first out behavior
Tree, hierarchical parent–child model
Queue, first in first out discipline
Linked list, pointer-based sequence
Which memory type requires UV light exposure to remove stored data before reprogramming?
SRAM, volatile cache storage
EEPROM, electrical erasure only
EPROM, ultraviolet erasure needed
PROM, permanently fixed contents
Select the structure that uses push and pop operations to manage elements.
Graph, add and explore
Stack, push and pop operations
Queue, enqueue and dequeue
Tree, insert and traverse
Which option best distinguishes EEPROM from Flash memory in typical usage?
Volatile behavior versus persistent behavior
Magnetic storage versus optical storage
Ultraviolet erasure versus thermal erasure
Byte-level erasure versus block-level erasure
A system must process tasks in arrival order to ensure fairness. Which data structure should be used?
Queue for arrival-order processing
Hash table for constant lookup
Stack for reverse-order handling
Tree for hierarchical scheduling
You need read-only firmware that can never be altered after manufacturing. Which memory is most appropriate?
RAM cleared when power off
PROM burned once at fabrication
EEPROM updated electrically
Flash memory rewritable blocks
Which action correctly describes removing the front element from a queue?
Shift removes last element
Delete removes random element
Pop removes top element
Dequeue removes front element
A developer must occasionally patch device configuration bytes without rewriting whole blocks. Which memory is ideal?
Flash for block-level updates
EEPROM for byte-level updates
PROM for single-time write
CD-ROM for optical read-only
Which claim about stacks and queues is accurate?
Stacks use LIFO; queues use FIFO
Stacks use FIFO; queues use LIFO
Both use FIFO access order
Both use LIFO access order
What is the average-case time complexity of Binary Search on a sorted array?
O(n) per search operation
O(n log n) overall time
O(log n) per search
O(1) constant time
Which operation in a queue removes the element at the front?
Pop from front end
Push from rear end
Dequeue from front
Enqueue into rear
Which of the following is NOT a linear data structure?
Queue with FIFO order
Tree with hierarchical nodes
Linked list of nodes
Array with fixed indexing
For Binary Search to work correctly, what precondition must hold for the data?
Data must be random
Data must be sorted
Data must be unique
Data must be large
What is the main difference between stack and queue removal operations?
Both use priority-based removal
Both use random access removal
Stack uses LIFO, queue uses FIFO
Stack uses FIFO, queue uses LIFO
Which scenario best suits Binary Search over Linear Search?
Dynamic streaming dataset
Small unsorted dataset
Sparse dataset with duplicates
Large sorted dataset
If a queue supports Enqueue and Dequeue, which additional operation most directly inspects the next removal?
Pop from top element
Peek at front element
Insert at front end
Push onto rear end
When analyzing algorithms, which complexity class indicates logarithmic growth in work?
O(n) linear growth
O(n^2) quadratic growth
O(1) constant growth
O(log n) logarithmic growth
Which invariant ensures correct mid-point narrowing in Binary Search?
Search window always expands
Pivot always moves to right
Indices are swapped each step
Low index never exceeds high
A queue implementation using a circular array prevents which common issue?
Duplicate elements insertion
Wasted slots after dequeues
Index overflow at rear
Memory fragmentation
In Selection Sort, which element is selected at each step while sorting elements in ascending order?
Any random element
The middle element
The smallest element
The largest element
What type of data structure is typically used to manage function calls during recursion?
Queue structure
Graph structure
Tree structure
Stack structure
Which data structure follows First-In, First-Out ordering for element processing?
Tree ordering
Heap ordering
Queue ordering
Stack ordering
Which data structure is best described by Last-In, First-Out removal of elements?
Queue removal
Stack removal
Table removal
List removal
During Selection Sort on an unsorted array, what is the primary operation performed after selecting the candidate element?
Enqueue for later use
Push onto recursion stack
Swap with current position
Insert candidate at front
In recursion, why is a stack preferred for tracking active calls?
Supports FIFO ordering
Supports breadth-first
Supports LIFO unwinding
Supports random access
Which structure naturally represents hierarchical relationships among elements?
Tree structure
Queue structure
Array structure
Stack structure
When implementing Selection Sort, what determines the element chosen during each pass for ascending order?
Arbitrary chosen value
Current largest value
Current smallest value
Median of subarray
A recursive algorithm terminates when which condition is met for its call stack?
Base case reached
No base case found
Tree becomes balanced
Queue becomes empty
Which statement best differentiates queue behavior from stack behavior?
Queues remove newest items
Stacks remove newest items
Both remove newest items
Neither removes newest items
Which sorting algorithm follows the divide-and-conquer paradigm?
Bubble sort with pairwise swaps
Selection sort with minimal picks
Merge sort with recursive splits
Insertion sort with incremental shifts
Which structure is not considered dynamic in typical implementations?
Array with fixed size allocation
Stack with linked nodes growth
Queue with dynamic linked storage
Tree with nodes inserted on demand
What operation pattern best characterizes a stack?
LIFO with top-based access
Random access with indices
FIFO with front removals only
Priority-based removal rules
In a queue, which access order is standard for removals?
Middle elements removed first
Highest-priority removed first
First-in elements removed first
Last-in elements removed first
Which data structure naturally supports hierarchical relationships?
Tree with parent-child links
Queue with linear ordering
Stack with single access point
Array with contiguous elements
Which scenario most benefits from a linked list over an array?
Constant-time range queries on slices
Fixed-size numeric matrix storage
Frequent random index lookups
Frequent middle insertions and deletions
Which statement best explains why merge sort is stable?
Swaps only adjacent unequal items
Selects minimum using strict ties
Merges halves preserving equal order
Inserts elements by shifting left
Which disadvantage is typical for arrays compared to linked lists?
Costly resizing for growth needs
Slow traversal of consecutive cells
Non-contiguous memory fragmentation
Higher pointer overhead per element
