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WorksheetsIntroduction and Learning Objectives
Total questions: 73
Worksheet time: 37mins
Which processor family is highlighted as an example of complex instruction set computers (CISCs)?
Intel x86 architecture
ARM architecture in phones
MIPS architecture variant
PowerPC consumer chips
What does the acronym RISC stand for in processor design?
Randomized Instruction Stream Controller
Reduced Instruction Set Computer
Rapid Instruction Sequencing Core
Reliable Integrated System Computation
Which statement best describes x86 according to the material?
Obsolete in supercomputing history
Result of decades of CISC design
Built only for embedded devices
Primarily a low-power RISC core
Select all characteristics or facts correctly associated with ARM in this material.
An example of CISC design
Known as a powerful RISC-based system
Used widely in embedded systems
Stands for Advanced RISC Machine
Which pair correctly matches family to design philosophy?
ARM → complex instruction set
x86 → complex instruction set
x86 → RISC approach
ARM → CISC approach
In terms of market share for non-embedded systems, which company has ranked number one for decades?
AMD across desktops
Qualcomm in laptops
ARM Ltd. in servers
Intel in non-embedded
Which description fits the role of x86 in the evolution of processor features?
Focused solely on minimal instruction sets
Designed only for mobile devices
Removes sophisticated features from computers
Brings mainframe principles to microprocessors
Choose all statements that are true about the two common processor families mentioned.
They are Intel x86 and ARM
Both are examples of RISC systems
They represent different design philosophies
ARM is prevalent in embedded applications
Which statement best defines an embedded system?
A network of cloud-based servers
A general-purpose desktop computer system
Electronics and software within a product
A stand-alone mechanical control device
Which everyday device most likely contains an embedded computing system?
Hand-cranked egg beater
Paper notebook
Wooden hammer
Cell phone
What role do sensors typically play in embedded systems?
Store program instructions
Measure external physical variables
Display output to users
Provide backup power supply
In the organization diagram, which component converts analog signals for the processor?
A/D conversion
D/A conversion
Memory module
Diagnostic port
Which two components in the diagram handle transformations between analog and digital forms?
A/D conversion
Custom logic
Human interface
D/A conversion
Which component stores data and instructions for the processor in the organization diagram?
Memory
Sensors
Actuators
Human interface
Which statement about embedded systems interaction is correct?
They replace all mechanical parts
They only run office applications
They never interact with physical variables
They sense and manipulate the external world
Which device from the examples list uses embedded systems in automotive applications?
Garden rake
Manual bicycle bell
Anti-lock brakes
Paper calendar
In the organization diagram, which component communicates system status for testing and troubleshooting?
Lighting system
Thermostat
Toothbrush
Diagnostic port
Which path correctly shows information flow from the environment to actions in the diagram?
Human interface → Memory → Sensors → Processor
Actuators → D/A → Processor → A/D → Sensors
Sensors → A/D → Processor → D/A → Actuators
Memory → Processor → Sensors → A/D → Actuators
Which item from the examples is NOT typically an embedded system?
Microwave oven
Digital camera
Tennis racket
Desktop general-purpose computer
Which statement best describes the origin of Intel’s company name?
Nickname of Robert Noyce
Acronym for Integrated Electronics
Named after Intelco acquisition
Short for Intelligent Computing
Who founded Intel after leaving Fairchild Semiconductor?
Robert Noyce and Gordon Moore
Steve Jobs and Steve Wozniak
Andy Grove and John Carmack
William Shockley and Ken Olsen
In which year was Intel founded as a new semiconductor company?
1968
1971
1974
1965
Which feature accurately characterizes the Intel 4004 microprocessor?
4-bit CPU with 740 kHz clock
16-bit CPU mainly used in PCs
4-bit CPU with direct interrupts
8-bit CPU with 800 kHz clock
What limitation did the Intel 4004 have compared to later chips?
Could not handle interrupts
Lacked any ROM support
No arithmetic logic unit
Zero external I/O capability
Which set lists components integrated with the Intel 4004 in one chip?
CPU, ROM, RAM, 10-bit shift register
CPU, GPU, RAM, cache memory
CPU, ROM, RAM, disk controller
CPU, FPU, RAM, network adapter
The Intel 4004 was mainly used in which type of devices?
Network routers
Calculators
Personal computers
Video game consoles
Which statements about the Intel 8008 are correct? Select all that apply.
Clock rate of 800 kHz
Handled interrupts
Direct memory addressing
First commercially available 8-bit CPU
Compared with the Intel 4004, what improvement did the Intel 8008 provide regarding the stack?
Bigger stack capacity
Hardware stack removal
Stack limited to two levels
Stack implemented off-chip only
Which I/O specification matches the Intel 8008?
16 input ports and 8 output ports
32 input ports and 4 output ports
4 input ports and 16 output ports
8 input ports and 24 output ports
Which memory capacity is associated with the Intel 8008 (ROM + RAM combined)?
64 KB
16 KB
4 KB
640 bytes
Which application areas commonly used the Intel 8008?
Digital cameras, drones, wearables
Audio mixers, printers, projectors
Mainframes, smartphones, servers
Calculators, industrial robots, terminals
Which processor helped establish what is known today as the x86 architecture and was used in the original IBM PC?
Pentium 4 desktop edition
Intel 80386 virtual mode unit
Intel 8088 original IBM PC
Intel 8080 microcomputer chip
What was a key innovation of the Intel 80386 that allowed running legacy 16-bit applications with protection to memory and resources?
Real Mode compatibility layer
Micro-ops fusion engine
Virtual Mode capability
Hyper-Threading feature
Which CPU is described as Intel’s first 32-bit x86 processor supporting up to 4 GB of memory?
Intel 8080 eight-bit chip
Intel 80386 thirty-two-bit
Pentium 4 sixty-four-bit
Intel 8088 sixteen-bit
The Intel 8080 introduced the stack pointer register. What practical effect did this have on program execution?
Provided dual-core processing
Added built-in graphics support
Let the stack grow to RAM size
Enabled floating-point arithmetic
Match each processor to its typical memory capacity noted at release.
Pentium 4: 128 KB total memory
80386: 4 GB total memory
8088: 1 MB total memory
8080: 64 KB total memory
Which statement about the Intel 8088’s specifications is accurate?
Up to 10 MHz clock speed
Eight-bit data bus processor
Four gigabytes memory support
Up to 40 MHz clock speed
Which processor marked the transition from 16-bit to broader 32-bit computing in personal computers?
Intel 8080 eight-bit era
Intel 8088 sixteen-bit era
Intel 80386 thirty-two-bit era
Core 2 Duo multi-core era
Which CPU was mainly used in early microcomputers and had a clock rate of 4 MHz?
Pentium 4 desktop systems
Intel 80386 personal computer
Intel 8088 IBM PC use
Intel 8080 microcomputer use
Select all processors in this set that are explicitly 16-bit or 32-bit designs.
Intel 8080 eight-bit design
Intel 8088 sixteen-bit design
Intel 80386 thirty-two-bit design
Pentium 4 sixty-four-bit design
Which feature or use aligns with Core 2 Duo compared to the earlier processors listed?
First commercial 16-bit CPU
Introduced Virtual Mode
Early multi-core consumer era
Used in original IBM PC
The original Intel 8088 supported a memory space totaling approximately:
64 KB ROM plus RAM
1 MB ROM plus RAM
4 GB ROM plus RAM
16 GB ROM plus RAM
Which processor specification correctly pairs clock speed with the CPU?
80386: up to 40 MHz
8088: 4 MHz fixed
Pentium 4: 1 MHz max
8080: up to 10 MHz
Which Core i7 generation introduced the codename Bloomfield and a shared L3 cache across four cores?
Haswell fourth
Ivy Bridge third
Sandy Bridge second
Nehalem first generation
What architectural change is most associated with Sandy Bridge compared to Nehalem?
Integrated graphics on-die
Split L1 cache per core
Reservation stations expanded
IPC gains through 22 nm
Which pair correctly matches generation to its hallmark improvement?
Ivy Bridge: IPC efficiency gains
Haswell: larger reservation stations
Sandy Bridge: integrated GPU
Nehalem: on-die memory controller
Nehalem’s cache hierarchy included which of the following features?
Shared L3 among four cores
Unified 8-way set L2 cache
Split 8-way set L1 cache
No prefetching in caches
In a quad-core Nehalem i7, how is the L3 cache arranged across cores?
Used only for graphics
Disabled by default
Dedicated per single core
Shared across all cores
Which generation most directly targeted increasing instructions per cycle (IPC)?
Haswell generation
Sandy Bridge generation
Nehalem generation
Ivy Bridge generation
Haswell improved out-of-order execution mainly by changes to what component?
Front-side bus speed
Main memory controller
Integrated graphics unit
Reservation stations structure
Which statements are true about Nehalem’s memory access design?
On-die memory controller reduced latency
Relied on external northbridge for RAM
No shared cache levels existed
Prefetching improved cache effectiveness
Choose the combination that best distinguishes Sandy Bridge and Ivy Bridge.
Sandy: new bus; Ivy: no cache
Sandy: larger L3; Ivy: split L1
Sandy: IPC gains; Ivy: reservation
Sandy: integrated GPU; Ivy: IPC gains
Which feature is least associated with Haswell among these options?
Integrated graphics emphasis
Out-of-order scheduling changes
Reservation stations refinement
Execution window adjustments
Which Intel Core i7 generation first introduced six-core mainstream models, increasing core counts compared to prior quad-core releases?
Coffee Lake processors
Broadwell generation models
Kaby Lake refresh chips
Skylake desktop lineup
As Core i7 evolved from Broadwell through Coffee Lake, how did L3 cache generally change to support more cores?
Moved entirely to L2 cache
Remained fixed per generation
Scaled up with core count
Shrank to reduce latency
Which pair of generations is often contrasted for architectural updates beyond process shrink, including cache behavior and efficiency?
Haswell vs Sandy Bridge
Kaby Lake vs Coffee Lake
Bloomfield vs Ivy Bridge
Broadwell vs Skylake
Kaby Lake’s cache strategy is best described as which of the following?
Major redesign increasing L2 size
Removal of shared L3 cache
Massive per-core cache doubling
Minor tuning of L3 policies
Which statement correctly links a generation to a cache or core-count characteristic?
Broadwell increased core counts in mainstream i7
Skylake refined cache hierarchy efficiency
Kaby Lake focused on small cache optimizations
Coffee Lake moved i7 to six cores
Why would L3 cache scaling be important as Intel increased core counts in later Core i7 generations?
To maintain shared data capacity
To store more instructions per core
To eliminate branch mispredictions
To reduce clock speeds safely
Which generation is most associated with the transition to six cores in mainstream Core i7 while keeping similar cache hierarchy?
Skylake
Coffee Lake
Kaby Lake
Broadwell
Choose the set that correctly orders generations discussed for later Core i7 iterations.
Broadwell, Coffee Lake, Kaby Lake
Coffee Lake, Skylake, Broadwell
Kaby Lake, Broadwell, Skylake
Skylake, Kaby Lake, Coffee Lake
Compared to Broadwell, what was a notable Skylake change relevant to cache and performance?
Redesigned microarchitecture efficiency
Removed shared L3 cache entirely
Added two extra physical cores
Switched to AMD cache layout
Which statements are true about cache size and later Core i7 generations?
Coffee Lake increased core counts to six
Kaby Lake made small cache refinements
L3 cache scaled to match more cores
Broadwell eliminated L3 cache entirely
Which Intel Core i7 generation introduced a modest IPC improvement alongside a larger L3 cache?
Coffee Lake generation reducing cache for speed
Kaby Lake generation eliminating L3 entirely
Skylake generation focused only on core clocks
Broadwell generation with IPC and L3 changes
Broadwell was released in early 2015 and saw about a 5% increase in IPC. What does IPC most directly affect in a CPU?
Total number of physical cores
Size of the integrated memory
Instructions executed per clock cycle
Maximum turbo power consumption
Which statement best explains why increasing L3 cache can improve performance in later Core i7 iterations?
It replaces L1 and L2 caches completely
It disables branch prediction logic entirely
It increases CPU core voltage automatically
It reduces main memory accesses for shared data
Compare Broadwell and Skylake regarding architecture evolution. Which is most accurate?
Broadwell replaced Skylake within months
Broadwell added cores beyond Skylake
Skylake refined Broadwell with efficiency gains
Skylake removed caches introduced in Broadwell
Kaby Lake is noted for cache behavior in the Core i7 line. Which description fits Kaby Lake?
Reduced L3 size to increase frequency
Eliminated shared L3 cache entirely
Introduced L4 cache for all desktops
Maintained L3 cache scaling strategy
Coffee Lake marked a major change in core counts for mainstream Core i7. What change occurred?
Increase to six physical cores
Addition of eight cores by default
Reduction to two physical cores
Fixed four cores with higher IPC
Which combination correctly pairs generation and characteristic?
Coffee Lake: six-core mainstream
Broadwell: ~5% IPC increase
Kaby Lake: cache scaling maintained
Skylake: architectural refinement
Why might Broadwell have been replaced within a few months despite improvements?
Lack of any cache in the design
Severe removal of integer units
Limited market success and rapid successor
Complete incompatibility with DDR4 memory
Which trend describes L3 cache across these Core i7 generations?
Shrank significantly each cycle
Removed then re-added later
Constant size without changes
Scaling with generation updates
A student claims Coffee Lake’s performance rise was mainly due to cache removal. What’s the best correction?
Improvement came from disabling IPC logic
Performance relied on dropping L1 cache
Performance improved with six cores added
Rise occurred by lowering base clock heavily
