WorksheetsPlacement Practice Test 2
Total questions: 100
Worksheet time: 50mins
Name
Class
Date
1.
A microcontroller is best described as:
a)
A CPU on a chip with dedicated peripherals and memory for control applications
b)
A general-purpose desktop processor
c)
An analog computational device
d)
A DSP specialized for audio only
2.
Which statement distinguishes a microprocessor from a microcontroller?
a)
Microprocessors typically require external memory and peripherals; microcontrollers integrate them on-chip
b)
Microprocessors always consume less power than microcontrollers
c)
Microcontrollers cannot be programmed in assembly language
d)
Microprocessors always use Harvard architecture
3.
Von Neumann architecture is characterized by:
a)
Shared program and data memory with a single bus
b)
Separate program and data memories with separate buses
c)
Parallel execution of multiple instruction streams
d)
Only analog memory
4.
Harvard architecture is characterized by:
a)
Separate program and data memories/buses allowing simultaneous access
b)
Shared memory for program and data on a single bus
c)
No instruction pipeline
d)
Only suitable for analog processing
5.
The classic Intel 8051 has how many pins?
a)
40
b)
28
c)
64
d)
20
6.
Which port of 8051 is open-drain and requires external pull-up resistors?
a)
Port 0
b)
Port 1
c)
Port 2
d)
Port 3
7.
PSEN (Program Store Enable) pin in 8051 is used for:
a)
Reading external program memory
b)
Writing to internal RAM
c)
Enabling serial port
d)
Resetting timers
8.
ALE (Address Latch Enable) in 8051 is primarily used to:
a)
Demultiplex address/data bus for external memory interfacing
b)
Enable interrupts
c)
Select register bank
d)
Start the watchdog
9.
The standard 8051 internal RAM size is:
a)
128 bytes
b)
256 bytes
c)
64 bytes
d)
1 KB
10.
Bit-addressable area in 8051 internal RAM spans:
a)
20H to 2FH (128 bits)
b)
00H to 07H (64 bits)
c)
80H to 8FH (SFRs)
d)
30H to 3FH (64 bits)
11.
Register banks in 8051 are located in internal RAM addresses:
a)
00H–1FH divided into four banks
b)
20H–2FH
c)
80H–FFH
d)
F0H–FFH only
12.
The default reset value of the 8051 Stack Pointer (SP) is:
a)
07H
b)
00H
c)
FFH
d)
10H
13.
Which register pair is used as a 16-bit data pointer in 8051?
a)
DPTR (DPH:DPL)
b)
SP
c)
PSW
d)
SCON
14.
Special Function Registers (SFRs) in 8051 are mapped to:
a)
Addresses 80H–FFH
b)
Addresses 00H–1FH
c)
Addresses 20H–2FH
d)
External memory only
15.
How many interrupt sources does the standard 8051 provide?
a)
5 (two external, two timer, one serial)
b)
3
c)
7
d)
2
16.
The 8051 interrupt priority is controlled by which SFR?
a)
IP
b)
IE
c)
PSW
d)
TMOD
17.
Interrupt enable bits in 8051 are set in which SFR?
a)
IE
b)
IP
c)
SCON
d)
TCON
18.
Timer/Counter Mode 1 in 8051 configures timers as:
a)
16-bit timers
b)
13-bit timers
c)
8-bit auto-reload timers
d)
Split timers
19.
Timer/Counter Mode 2 in 8051 configures timers as:
a)
8-bit auto-reload timers
b)
16-bit timers
c)
13-bit timers
d)
One-shot timers
20.
Which SFR sets timer modes in 8051?
a)
TMOD
b)
TCON
c)
SCON
d)
PCON
21.
Which bits start the timers in 8051?
a)
TR0 and TR1 in TCON
b)
TF0 and TF1 in TCON
c)
ET0 and ET1 in IE
d)
SM0 and SM1 in SCON
22.
Serial port pins of 8051 are:
a)
RxD (P3.0) and TxD (P3.1)
b)
SDA and SCL
c)
MOSI and MISO
d)
INT0 and INT1
23.
8051 serial port Mode 1 provides:
a)
8-bit UART with variable baud rate
b)
9-bit UART with fixed baud
c)
Shift register mode
d)
Synchronous serial
24.
Baud rate in 8051 UART Mode 1 is commonly generated using:
a)
Timer 1 overflow rate
b)
Timer 0 capture
c)
External crystal directly without divider
d)
PWM module
25.
Instruction MOVX is used to access:
a)
External data memory
b)
Internal RAM
c)
Program memory
d)
SFRs
26.
Instruction MOVC A,@A+DPTR accesses:
a)
Code (program) memory using indexed addressing
b)
External data memory
c)
Bit-addressable RAM
d)
SFR bank
27.
Which addressing mode uses @R0 or @R1 in 8051?
a)
Register indirect
b)
Immediate
c)
Direct
d)
Indexed
28.
Which instruction is used for looping with automatic decrement?
a)
DJNZ
b)
CJNE
c)
SJMP
d)
JNB
29.
Port 3 pins P3.2 and P3.3 are typically used for:
a)
External interrupts INT0 and INT1
b)
Serial data lines
c)
Timer outputs
d)
I2C bus
30.
Which statement about PWM on 8051 is correct?
a)
PWM can be generated by toggling an output in timer/interrupt routines
b)
8051 has a dedicated hardware PWM unit
c)
PWM cannot be generated on 8051
d)
PWM requires external DAC only
31.
I2C bus uses which lines?
a)
SDA and SCL
b)
MOSI and MISO
c)
TxD and RxD
d)
TCK and TMS
32.
LM35 sensor outputs:
a)
10 mV/°C analog voltage proportional to temperature
b)
Digital I2C temperature data
c)
PWM proportional to temperature
d)
Resistance change like an LDR
33.
LDR is primarily a:
a)
Light-dependent resistor whose resistance decreases with light
b)
Temperature sensor
c)
Hall-effect sensor
d)
Piezoelectric sensor
34.
In 8051 C programming, accessing Port 1 typically uses:
a)
P1 register (e.g., P1 = 0xFF;)
b)
printf()
c)
scanf()
d)
PSW
35.
A continuous-time signal x(t) is called even if:
a)
x(t) = x(-t)
b)
x(t) = -x(-t)
c)
x[n] = x[-n]
d)
x(t) = 0
36.
A discrete-time signal x[n] is causal if:
a)
x[n] = 0 for n < 0
b)
x[n] = 0 for n > 0
c)
It is periodic in n
d)
Its Fourier transform exists
37.
Time shifting of a signal x(t) by t0 results in:
a)
x(t - t0)
b)
x(t + t0)
c)
x(t) + t0
d)
t0 * x(t)
38.
A system is BIBO stable if:
a)
Every bounded input produces a bounded output
b)
Its output is always zero
c)
It is linear and time-invariant
d)
It has memory
39.
Convolution of x(t) and h(t) for CT LTI systems is given by:
a)
y(t) = ∫ x(τ) h(t − τ) dτ
b)
y(t) = x(t) · h(t)
c)
y(t) = x(t) + h(t)
d)
y(t) = x(t)/h(t)
40.
Linear convolution for discrete-time signals is:
a)
y[n] = Σ x[k] h[n − k]
b)
y[n] = x[n] · h[n]
c)
y[n] = x[n] + h[n]
d)
y[n] = x[n]/h[n]
41.
Fourier series represents:
a)
Periodic continuous-time signals as sums of harmonically related sinusoids
b)
Aperiodic signals only
c)
Random signals only
d)
Discrete-time signals only
42.
Gibbs phenomenon refers to:
a)
Oscillations near discontinuities in Fourier series approximations
b)
Aliasing due to sampling below Nyquist rate
c)
Noise amplification in filters
d)
Window leakage in DTFT
43.
Laplace transform X(s) converges in a region called:
a)
Region of Convergence (ROC)
b)
Nyquist region
c)
Z-plane
d)
Time domain
44.
For a stable causal CT LTI system, the ROC of H(s) is:
a)
Right half-plane to the right of the rightmost pole (includes jω-axis)
b)
Left half-plane including all poles
c)
Between zeros only
d)
A circle of radius 1
45.
Relationship between Fourier and Laplace transforms:
a)
Fourier transform is the Laplace transform evaluated on the jω-axis if ROC includes it
b)
Laplace is the Z-transform of sampled signals
c)
They are unrelated
d)
Fourier is the derivative of Laplace
46.
Transfer function H(s) is defined as:
a)
Ratio of output to input in the Laplace domain for zero initial conditions
b)
Sum of output and input
c)
Product of output and input
d)
Difference equation coefficients
47.
Frequency response of an LTI system is obtained by:
a)
Evaluating H(jω)
b)
Taking inverse Laplace
c)
Differentiating H(s)
d)
Integrating h(t)
48.
Sampling theorem states that a bandlimited signal of bandwidth B Hz can be reconstructed if sampled at:
a)
fs ≥ 2B
b)
fs ≥ B/2
c)
fs ≤ B
d)
fs = B
49.
Aliasing occurs when:
a)
Sampling frequency is below Nyquist rate causing spectral overlap
b)
Sampling frequency is very high
c)
Signal is strictly periodic
d)
Signal is strictly aperiodic
50.
Ideal reconstruction of a sampled CT signal uses:
a)
An ideal low-pass (sinc) interpolation filter
b)
High-pass filter
c)
Bandstop filter
d)
No filter
51.
Discrete-Time Fourier Series (DTFS) represents:
a)
Finite-length periodic discrete-time signals
b)
Aperiodic continuous-time signals
c)
Random processes only
d)
CT periodic signals
52.
DTFT of a sequence is:
a)
A periodic function of frequency with period 2π
b)
Non-periodic in frequency
c)
Always a delta function
d)
Always real-valued
53.
Time-shifting property in DTFT:
a)
x[n − n0] ↔ e^{−jω n0} X(e^{jω})
b)
x[n − n0] ↔ X(e^{jω})
c)
x[n] ↔ X(e^{jω − n0})
d)
x[n] ↔ e^{jω n0} X(e^{jω})
54.
Z-transform X(z) of x[n] is:
a)
Σ x[n] z^{−n}
b)
∫ x(t) e^{−st} dt
c)
Σ x[n] e^{jωn}
d)
Integral of x[n]
55.
For a causal discrete-time LTI system, ROC of H(z) is:
a)
Outside the outermost pole
b)
Inside the innermost pole
c)
Between zeros only
d)
Exactly the unit circle only
56.
Stability in the Z-domain requires:
a)
ROC includes the unit circle
b)
ROC is outside all poles
c)
ROC excludes the unit circle
d)
No poles
57.
Unilateral Z-transform is useful for:
a)
Handling initial conditions and one-sided sequences
b)
Periodic signals only
c)
Random signals only
d)
Fourier series
58.
Difference equation representation of DT systems relates:
a)
Current output to past outputs and inputs via coefficients
b)
Fourier coefficients only
c)
Only current input to current output
d)
Poles only
59.
Convolution property in Z-domain:
a)
y[n] = x[n]*h[n] ↔ Y(z) = X(z) H(z)
b)
y[n] ↔ X(z) + H(z)
c)
y[n] ↔ X(z)/H(z)
d)
y[n] ↔ X(z) − H(z)
60.
Magnitude response of a DT LTI system is:
a)
|H(e^{jω})|
b)
∠H(e^{jω})
c)
H(s)
d)
h[n]
61.
Causality of a CT LTI system is ensured when:
a)
Impulse response h(t) = 0 for t < 0
b)
h(t) = 0 for t > 0
c)
h[n] = 0 for n < 0
d)
ROC includes unit circle
62.
Orthogonality of signals x1(t) and x2(t) over [a,b] means:
a)
∫ x1(t) x2(t) dt = 0 over [a,b]
b)
x1(t) = x2(t)
c)
They are periodic
d)
They have same energy
63.
Energy of a signal x(t) is defined as:
a)
∫ |x(t)|^2 dt
b)
∫ x(t) dt
c)
max(x(t))
d)
Σ x[n]
64.
DTFT to Z-transform relation:
a)
DTFT is Z-transform evaluated on the unit circle z = e^{jω} when ROC includes it
b)
DTFT is Laplace transform
c)
Z-transform is Fourier series
d)
No relation
65.
Top-down design methodology emphasizes:
a)
Starting from system-level specifications and refining to lower levels
b)
Starting from transistor-level and building up
c)
Random prototyping only
d)
Mask fabrication first
66.
Bottom-up methodology emphasizes:
a)
Building complex systems from verified lower-level blocks upward
b)
Beginning with system specs only
c)
Only software design
d)
Skips verification
67.
Full-custom ASICs are characterized by:
a)
Transistor-level layout optimized for performance/area/power
b)
Use of pre-designed standard cells only
c)
No layout
d)
Gate arrays only
68.
Standard cell-based ASICs use:
a)
Pre-characterized logic cells placed and routed
b)
Only programmable logic
c)
No synthesis tools
d)
Analog-only blocks
69.
Gate array-based ASICs are:
a)
Pre-diffused arrays customized by metallization layers
b)
Built entirely from FPGAs
c)
Always full-custom
d)
Only analog designs
70.
PLAs differ from PALs primarily in:
a)
Both programmable AND and OR planes in PLA; PAL typically has fixed OR
b)
PLA is always faster
c)
PAL is always larger
d)
No difference
71.
FPGAs are best described as:
a)
Field-programmable gate arrays with configurable logic blocks and interconnect
b)
Fixed-function ASICs
c)
Analog circuit arrays
d)
Microcontrollers
72.
In a CMOS inverter, the pull-up device is:
a)
PMOS
b)
NMOS
c)
BJT
d)
Diode
73.
Noise margins and DC transfer characteristics of a CMOS inverter depend on:
a)
Transistor sizing and threshold voltages
b)
Only supply wiring
c)
Package type only
d)
Temperature alone
74.
Switching characteristics of a CMOS inverter are influenced by:
a)
Load capacitance and transistor resistance
b)
Only DC power
c)
ROM size
d)
Clock frequency alone
75.
Power dissipation in CMOS is mainly due to:
a)
Dynamic power from charging/discharging capacitances and leakage (static) power
b)
Only static power
c)
Only short-circuit power
d)
No power consumption
76.
Pass-transistor logic uses:
a)
Transistors as transmission elements to pass logic levels
b)
Only inverters
c)
BJT differential pairs
d)
ROM cells
77.
A transmission gate is:
a)
Parallel NMOS and PMOS controlled complementarily to pass both 0 and 1 efficiently
b)
Single NMOS used alone
c)
Single PMOS used alone
d)
A diode network
78.
Layout design rules ensure:
a)
Manufacturability and yield by constraining widths, spacings, and overlaps
b)
Only faster designs
c)
Only smaller area
d)
Only aesthetics
79.
Stick diagrams are used for:
a)
Quick, color-coded representation of layout topology without exact dimensions
b)
Exact mask generation
c)
Schematic capture only
d)
Timing simulation
80.
Dynamic logic employs precharge and evaluate phases to:
a)
Reduce area and increase speed compared to static logic
b)
Eliminate leakage completely
c)
Simplify clocking always
d)
Avoid capacitive loads
81.
Domino logic typically uses:
a)
Dynamic NMOS evaluation network with static CMOS inverter stages
b)
Only PMOS networks
c)
Bipolar transistors
d)
ROM arrays
82.
Content Addressable Memory (CAM) supports:
a)
Search by content (associative lookup)
b)
Only sequential addressing
c)
Analog storage
d)
No parallelism
83.
A 6T SRAM cell stores data using:
a)
Two cross-coupled inverters and two access transistors
b)
One capacitor only
c)
Flash floating-gate
d)
Resistive elements only
84.
A 1T1C DRAM cell stores data as:
a)
Charge on a capacitor accessed by a single transistor
b)
Magnetization state
c)
Phase change in chalcogenide
d)
Resistance of an oxide
85.
EPROM, EEPROM, and Flash are:
a)
Non-volatile memories based on floating-gate transistors
b)
Volatile SRAM types
c)
Magnetic memories only
d)
Optical memories
86.
HBM (High Bandwidth Memory) primarily offers:
a)
3D-stacked DRAM with wide interface for high throughput
b)
On-chip SRAM arrays only
c)
Magnetic storage
d)
Optical interconnects only
87.
Emerging memories such as MRAM, RRAM, PCM store data via:
a)
Magnetization, resistive switching, and phase change respectively
b)
Only electric charge
c)
Only optical states
d)
Only mechanical states
88.
A carry-lookahead adder improves speed by:
a)
Computing carry signals in parallel using generate/propagate logic
b)
Serially rippling carries
c)
Using analog addition
d)
Reducing bit-width
89.
Kogge–Stone adder is a:
a)
Parallel prefix adder with log2(N) depth and high wiring complexity
b)
Ripple-carry adder
c)
Analog adder
d)
Serial adder
90.
Array multiplier is characterized by:
a)
Regular structure formed by add-and-shift partial products
b)
Wallace tree reduction of partial products
c)
Booth recoding of operands
d)
Time-multiplexed single adder
91.
Wallace tree multiplier reduces:
a)
Partial products using carry-save compressors to shorten critical path
b)
Power using gating only
c)
Operand width
d)
Memory size
92.
Booth multiplication technique:
a)
Recodes multiplier bits to reduce number of partial products
b)
Uses only serial addition
c)
Is purely analog
d)
Eliminates adders entirely
93.
Modified Booth (radix-4) encoding groups bits to:
a)
Encode pairs (with overlap) to generate ±0, ±1, ±2 multiples
b)
Encode single bits only
c)
Generate only +1 multiples
d)
Always doubles bit-width
94.
CZ (Czochralski) process is used for:
a)
Crystal growth to produce silicon ingots
b)
Photolithography mask writing
c)
Ion implantation
d)
Wet oxidation only
95.
Thermal oxidation of silicon grows:
a)
SiO2 insulating layer on silicon surface
b)
Si3N4 layer by default
c)
Metal layer
d)
Poly-Si gate directly
96.
Ion implantation is primarily used to:
a)
Introduce dopant atoms with controlled energy and dose
b)
Grow epitaxial layers
c)
Pattern photoresist
d)
Deposit metal interconnects
97.
Molecular Beam Epitaxy (MBE) is a technique for:
a)
Epitaxial growth of thin crystalline layers under ultra-high vacuum
b)
Wet oxidation
c)
Dry etching only
d)
CMP (planarization)
98.
Photolithography sequence includes:
a)
Coat photoresist, align/expose, develop, etch/deposit, strip
b)
Ion implant, grow oxide, metallize, CMP
c)
Only etching
d)
Only deposition
99.
In an N-well CMOS process:
a)
PMOS transistors are formed in N-wells; NMOS in P-type substrate
b)
NMOS in N-wells; PMOS in P-wells
c)
Both NMOS and PMOS in N-wells
d)
Only NMOS devices are possible
100.
RS-232 electrical levels between DTE and DCE are approximately:
a)
±3V to ±15V (typically ±12V)
b)
0V to 5V TTL
c)
0V to 3.3V CMOS
d)
Only differential LVDS
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